Hybrid Gate Level Simulation for Circuit Design Verification
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Solution Overview
Problem
Existing circuit design verification methodologies are inefficient for large and complex synthesized designs, as they either alter the original design intent or impose limitations to achieve faster verification, leading to challenges in detecting functional issues and reducing simulation time.
Innovation Solution
A hybrid Gate Level Simulation (GLS) methodology that combines RTL and synthesized Netlist partitions, using interface and connectivity mapping, and prediction techniques to replace selected RTL partitions with their equivalent Netlist partitions, allowing for scalable technology that models final manufactured hardware products, thereby reducing simulation time and identifying design errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Gate Level Simulation is performed on large synthesized designs, then verification accuracy is improved, but simulation time increases significantly
Solution Approach 1:
The patent divides the large synthesized design into multiple smaller partitions or chunks, allowing the simulation to process each partition separately and in parallel. This segmentation maintains verification accuracy on each partition while reducing the overall simulation time by enabling concurrent processing of multiple partitions.
Solution Approach 2:
The patent introduces a new dimension of parallel processing by executing simulations across multiple partitions simultaneously. Instead of processing the entire design sequentially in one dimension, the methodology adds a parallel execution dimension, transforming the simulation approach from serial to concurrent processing.
2Loss of time
If RTL design simulation is performed, then simulation time is reduced, but verification effectiveness decreases for synthesized designs
Solution Approach 1:
The patent applies different simulation approaches to different parts of the design. Critical synthesized portions are simulated at gate level to maintain verification effectiveness, while less critical areas may use faster simulation methods. This local quality differentiation ensures verification effectiveness where needed while maintaining overall simulation efficiency.
Solution Approach 2:
The patent changes the simulation parameters and granularity by working with partitioned synthesized netlists rather than complete designs. By adjusting the scope and granularity parameters of simulation to match partitioned designs, the methodology achieves both reduced simulation time and maintained verification effectiveness for the synthesized portions.
3Loss of time
If existing partitioning methods are used to speed up simulation, then simulation time is reduced, but design intent is altered or lost
Solution Approach 1:
The patent performs preliminary actions by creating accurate partitions of the synthesized netlist before simulation begins. The partitioning methodology preserves design intent by maintaining the structural relationships and connectivity information from the original synthesized design, ensuring that subsequent parallel simulations reflect the actual design intent rather than artificial abstractions.
Data Source
AI summary
Examples described herein relate to at least one processor and at least one memory comprising instructions stored thereon, that if executed by the at least one processor, cause the at least one processor to access partitions representative of a first circuit representation, map at least one port representation of at least one partition of the partitions representative of the first circuit representation to at least one port of a second circuit representation based on a stored mapping of the at least one port representation of at least one partition of the partitions representative of the first circuit representation to the at least one port of a second circuit representation, and output the at least one single bit port representation of the at least one port of a second circuit representation.