Hybrid Gate Mask Structure for Precise Contact Etching
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in protecting gate structures during the formation of contacts to source/drain regions, leading to issues such as voids in gate masks and increased damage, which affect yield and performance.
Innovation Solution
The formation of gate masks with a hybrid film structure comprising a dielectric layer and a semiconductor layer, where the semiconductor layer is planarized to be coplanar with an interlayer dielectric, allowing for controlled etching of the interlayer dielectric while preserving the gate mask, reducing parasitic capacitance and enhancing etching efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate mask structure is used during contact formation, then the gate structure can be protected to some extent, but voids form in the gate mask and damage to the gate structure increases
Solution Approach 1:
The gate mask is formed as a composite structure with a first material layer (e.g., silicon nitride) and a second material layer (e.g., silicon oxide or silicon oxynitride). This composite structure provides both protection for the gate structure and resistance to etching, preventing void formation while maintaining integrity during contact opening formation.
Solution Approach 2:
The etching process parameters are optimized to achieve selective removal of the interlayer dielectric material while preserving the gate mask structure. By controlling etch selectivity between the interlayer dielectric and the gate mask materials, the process prevents damage to the gate structure while forming precise contact openings.
2Reliability
If the gate mask is made more protective, then gate structure damage is reduced, but etching efficiency decreases and parasitic capacitance increases
Solution Approach 1:
The composite gate mask structure uses materials with different etching resistances. The first material layer provides strong protection, while the second material layer allows controlled etching progression. This enables efficient removal of the interlayer dielectric without compromising gate structure protection.
Solution Approach 2:
Different regions of the gate mask have different material compositions optimized for their specific functions. The first material layer is positioned where maximum protection is needed, while the second material layer is configured to facilitate controlled etching, creating local quality variations that balance protection and etching efficiency.
3Productivity
If feature sizes are reduced to increase integration density, then more components can be integrated, but gate mask voids and structural damage increase
Solution Approach 1:
The composite gate mask structure maintains structural integrity at reduced feature sizes by distributing mechanical and chemical stresses across multiple material layers. This prevents void formation even when dimensions are scaled down, enabling high integration density while maintaining device yield.
Solution Approach 2:
The gate mask is segmented into multiple material layers, each performing specific functions. This segmentation allows the structure to better withstand the challenges of miniaturization, as each layer can be optimized for its specific role in protecting the gate structure during contact formation at reduced feature sizes.
Data Source
AI summary
A method of forming a semiconductor device includes forming a source/drain region over a substrate; forming a first interlayer dielectric over the source/drain region; forming a gate structure over the substrate and laterally adjacent to the source/drain region; and forming a gate mask over the gate structure, the forming the gate mask comprising: etching a portion of the gate structure to form a recess relative to a top surface of the first interlayer dielectric; depositing a first dielectric layer over the gate structure in the recess and over the first interlayer dielectric; etching a portion of the first dielectric layer; depositing a semiconductor layer over the first dielectric layer in the recess; and planarizing the semiconductor layer to be coplanar with the first interlayer dielectric.