Hybrid Gate Spacer Structure for Lower FET Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As transistors shrink, parasitic capacitance increases due to reduced lateral spacing between the gate and source/drain terminals, and existing dielectric materials with lower relative permittivity lack robustness in CMOS processing, limiting the integration of low-k dielectric materials with k-value below 5.0.
Innovation Solution
A hybrid gate spacer is introduced, comprising a low-k dielectric material with a relative permittivity below 5.0, protected by additional dielectric materials of higher permittivity, which reduces parasitic capacitance while maintaining robustness through the spacer cap and inner/outer dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If low-k dielectric material with relative permittivity below 5.0 is used in gate spacer, then parasitic capacitance is reduced, but material robustness to downstream processing deteriorates
Solution Approach 1:
The patent applies composite materials by combining low-k dielectric material (for low parasitic capacitance) with protective dielectric materials (for processing robustness) to form a hybrid gate spacer structure. This composite approach allows the spacer to simultaneously achieve low capacitance and withstand downstream processing steps.
Solution Approach 2:
The gate spacer is segmented into multiple functional layers: a low-k dielectric material layer (for capacitance reduction) and protective dielectric material layers (for processing robustness). This segmentation allows each layer to perform its specific function independently while working together as a unified structure.
2Productivity
If lateral spacing between gate and source/drain terminals is reduced, then transistor density is improved, but parasitic capacitance increases
Solution Approach 1:
The patent changes the dielectric parameter (relative permittivity) of the gate spacer material by using low-k dielectric material with permittivity below 5.0. This parameter change reduces the parasitic capacitance associated with the gate spacer, allowing tighter lateral spacing without proportionally increasing capacitance.
3Power
If vertical height of gate and source/drain terminals is increased, then transistor performance is improved, but parasitic capacitance increases
Solution Approach 1:
The hybrid gate spacer uses composite materials where the low-k dielectric component specifically addresses the capacitance issue arising from increased vertical dimensions, while the protective dielectric component ensures structural integrity. This allows taller structures to be built without proportionally increasing parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hybrid spacer achieves lower parasitic capacitance than conventional spacers while remaining robust to downstream processing, enhancing transistor performance by reducing capacitance without compromising material integrity.
Implementation Method 1
parasitic capacitance associated with the gate spacer is also a function of relative permittivity of the dielectric material employed
Data Source
AI summary
A FET including a hybrid gate spacer separating a gate electrode from at least one of a source, a drain, or source/drain contact metallization. The hybrid spacer may include a low-k dielectric material for a reduction in parasitic capacitance. The hybrid spacer may further include one or more other dielectric materials of greater relative permittivity that may protect one or more surfaces of the low-k dielectric material from damage by subsequent transistor fabrication operations. The hybrid spacer may include a low-k dielectric material separating a lower portion of a gate electrode sidewall from the source/drain terminal, and a dielectric spacer cap separating to an upper portion of the gate electrode sidewall from the source/drain terminal. The hybrid spacer may have a lower total capacitance than conventional spacers while still remaining robust to downstream fabrication processes. Other embodiments may be described and/or claimed.