Hybrid Gate Stack Integration for Stacked Vertical Transistors
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Solution Overview
Problem
Conventional semiconductor fabrication techniques face challenges in scaling down gate lengths and device sizes, particularly in stacking field-effect transistors, as they reach the limits of miniaturization, necessitating innovative approaches for further density and performance enhancements.
Innovation Solution
The implementation of hybrid gate stack integration in stacked vertical transport field-effect transistor structures, where the same gate conductor material, such as titanium nitride, is used for both upper and lower transistors, employing different annealing techniques and processing flows for the gate-first and gate-last processes, respectively, to optimize device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional semiconductor fabrication techniques are used for stacking field-effect transistors, then existing manufacturing processes can be maintained, but device scaling and density enhancement are limited
Solution Approach 1:
The transistor structure is divided into multiple stacked layers with separate gate stacks for upper and lower transistors. Each gate stack is formed independently through distinct processing flows (gate-first for lower, gate-last for upper), enabling precise control of each segment while achieving high overall density
Solution Approach 2:
The patent transitions from planar transistor arrangements to vertical stacking in the third dimension. Multiple transistors are stacked vertically with isolation layers between them, dramatically increasing device density without further reducing gate length
2Reliability
If different gate conductor materials are used for upper and lower transistors, then each transistor can be optimized independently, but manufacturing complexity and process steps increase
Solution Approach 1:
The same gate conductor material (e.g., titanium nitride) is used for both upper and lower transistors, providing universal material properties while achieving different device characteristics through distinct processing flows (gate-first vs. gate-last) and annealing techniques
Solution Approach 2:
Different annealing techniques are applied to the same gate conductor material depending on its location: rapid thermal annealing for the lower transistor gate and laser annealing for the upper transistor gate, creating locally optimized properties from a universal material
3Reliability
If gate-first process is used for lower transistor, then lower transistor performance is optimized, but upper transistor formation becomes more complex
Solution Approach 1:
The lower transistor gate stack is formed first through the gate-first process with preliminary annealing and doping steps. This preliminary action establishes a stable foundation that enables subsequent upper transistor formation without compromising the already-optimized lower device
4Productivity
If device size is reduced for scaling, then more devices can be integrated, but manufacturing precision and reliability deteriorate
Solution Approach 1:
Instead of continuing to reduce lateral dimensions, the patent stacks transistors vertically in the third dimension. This maintains larger, more manufacturable gate lengths while achieving high integration density through vertical arrangement with isolation layers
Solution Approach 2:
The vertical stack is segmented into distinct upper and lower transistor regions with separate gate stacks and isolation layers. This segmentation allows each transistor to be manufactured with adequate dimensions while achieving high overall integration through vertical stacking
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient integration of stacked vertical transport field-effect transistors, allowing for further device scaling, improved density, performance, and reduced power consumption, while maintaining reliability and integration advantages.
Implementation Method 1
employing different annealing techniques and processing flows for the gate-first and gate-last processes
Data Source
AI summary
A method of forming a semiconductor structure includes forming one or more vertical fins each including a first semiconductor layer providing a vertical transport channel for a lower vertical transport field-effect transistor (VTFET) of a stacked VTFET structure, an isolation layer over the first semiconductor layer, and a second semiconductor layer over the isolation layer providing a vertical transport channel for an upper VTFET of the stacked VTFET structure. The method also includes forming a first gate stack including a first gate dielectric layer and a first gate conductor layer surrounding a portion of the first semiconductor layer of the vertical fins. The method further includes forming a second gate stack including a second gate dielectric layer and a second gate conductor layer surrounding a portion of the second semiconductor layer of the vertical fins. The first gate conductor layer and the second gate conductor layer are the same material.