Hybrid Graphics Pipeline With Mocked Present for Frame Latency
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Solution Overview
Problem
The latency in data transport between semiconductor chips in computing devices reduces performance and utilization of processing nodes due to dependencies in workload processing, particularly in applications like parallel data graphics where one chip waits for results from another before proceeding.
Innovation Solution
Implementing a private queue synchronization mechanism that generates synchronization signals based on the completion of data processing on a dedicated GPU, allowing the next iteration of the loop to begin earlier, thus removing data transport latency unbeknownst to the host CPU.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transport latency is reduced by allowing next iteration to begin earlier, then processing performance and utilization increase, but data integrity and synchronization reliability may be compromised
Solution Approach 1:
The dedicated processing circuit generates a completion indication before the data transfer is fully complete, allowing the host processing circuit to proceed with the next iteration early. This preliminary action eliminates the blocking wait and improves productivity while the actual data transfer completes in the background.
Solution Approach 2:
A completion indication mechanism acts as an intermediary between the dedicated processing circuit and the host processing circuit. This intermediary allows the host to know when processing is complete without requiring direct data transfer completion as a blocking condition, thus improving performance while maintaining synchronization reliability through proper signaling.
2Reliability
If the first semiconductor chip waits for results from the second semiconductor chip, then data integrity is ensured, but processing throughput and chip utilization decrease
Solution Approach 1:
The dedicated processing circuit generates the completion indication in advance of the actual data being fully processed or transferred. This allows the host to proceed without waiting for data transfer completion, thereby increasing throughput while the completion indication ensures data integrity is maintained through proper synchronization signaling.
Solution Approach 2:
By using the completion indication to unblock the wait synchronization point early, the host processing circuit can continue with the next iteration without interruption. This maintains continuous useful action and improves throughput, while the dedicated circuit ensures data integrity through the synchronization mechanism.
3Reliability
If traditional work queue synchronization is used, then data synchronization is reliable, but processing latency and time consumption increase
Solution Approach 1:
The dedicated processing circuit generates the completion indication before the data transfer is complete, allowing the host to proceed early. This preliminary generation of the synchronization signal eliminates the time loss associated with waiting for data transfer completion while maintaining reliable synchronization through the work queue mechanism.
Solution Approach 2:
The completion indication serves as an intermediary that decouples the synchronization wait from the actual data transfer completion. This allows reliable synchronization to be maintained while reducing processing latency, as the host can proceed based on the indication rather than blocking for data transfer completion.
Data Source
AI summary
An apparatus and method for efficiently managing jobs of a workload performed among multiple integrated circuits in separate semiconductor chips. In various implementations, a computing system includes a first processing node and a second processing node that together render and present video frame data. The graphics application holds the start of processing the next video frame until the first processing node receives result data for the current video frame from the second processing node and presents the video frame data. To remove latency, once the result data is generated, the first processing node performs a mocked present job visible to the operating system scheduler but sends no data to the display controller. The rendering of the next video frame begins, and the first processing node later presents the result data to the display controller.