Hybrid Hard Mask for Semiconductor Interconnects

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Solution Overview

Problem

Conventional interconnect processing in semiconductor fabrication faces challenges with shrinking dimensions, leading to unreliable connections due to over-cutting and alignment issues, especially as the pitch of metal lines decreases, making it difficult to form accurate openings without cutting neighboring lines.

Innovation Solution

A method involving a mask stack with multiple layers and self-aligned protecting structures is used to form hybrid hard masks, allowing for the etching of recesses without cutting metal lines, thereby eliminating the need for precise alignment and reducing process complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional cuts/openings are formed to separate metal lines, then metal line separation is achieved, but alignment precision deteriorates and neighboring lines are inadvertently cut

Engineering Contradiction:
Improveopening formation precisionVSAvoidinterconnection reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The invention segments the mask structure into multiple layers (first mask layer, second mask layer, third mask layer) with each layer serving specific functions. The first mask layer defines the metal line pattern, the second mask layer forms the cutting pattern, and the third mask layer provides alignment reference. This segmentation allows independent optimization of each layer's function, enabling precise metal line separation without compromising alignment accuracy or cutting neighboring lines.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention performs preliminary actions by forming the first mask layer and third mask layer before forming the second mask layer. The first mask layer is used to define the metal line pattern, and the third mask layer is used to form alignment marks. These preliminary structures serve as references for subsequent processing steps, ensuring that the cutting openings are formed with high precision without cutting neighboring lines.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If tight overlay margins are used to prevent over-cutting, then neighboring lines are protected, but process complexity increases

Engineering Contradiction:
Improveinterconnection reliabilityVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention introduces a third mask layer as an intermediary that provides alignment marks for subsequent processing steps. This intermediary layer acts as a reference guide, allowing the second mask layer to be aligned precisely with the first mask layer's metal line pattern. The alignment marks serve as mediators between different mask layers, eliminating the need for tight overlay margins and simplifying the alignment process.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If opening size is increased to ensure metal line cutting, then cutting reliability improves, but neighboring lines are inadvertently cut

Engineering Contradiction:
Improvecutting reliabilityVSAvoidline separation precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The invention applies local quality by making the mask layers selectively removable at different locations. The second mask layer is designed to be selectively removable only at specific cutting locations defined by the first mask layer, while remaining intact over neighboring lines. This localized removal approach allows reliable cutting at intended locations without affecting adjacent metal lines, achieving both cutting reliability and line separation precision.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11120996B2Method for preparing a semiconductor structure
Publication Date: 2021.09.14 NAN YA TECH
  • US11120996B2 patent drawing
  • US11120996B2 patent drawing
  • US11120996B2 patent drawing

AI summary

The present disclosure provides a method for preparing a semiconductor structure. The method includes the following steps. A mask stack including a first mask and a second mask is formed on a substrate. Core patterns are formed over the mask stack. Spacers are formed over sidewalls of each core pattern. A patterned layer, including first openings, is formed over the core patterns and the spacers. Portions of the core patterns, the spacers and the second mask exposed through the first openings are removed to form second openings for accommodating self-aligned protecting structures. The core patterns are removed to form third masks. Portions of the second mask exposed through the third masks and the self-aligned protecting structures are removed to form third openings. Portions of the first mask exposed through the third openings are removed to form a hybrid hard mask. The substrate is then etched through the hybrid hard mask.