Hybrid Hardware-Software Placement for EDA Timing Accuracy
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Solution Overview
Problem
Current hardware-assisted placement techniques for electronic design automation are inefficient and inaccurate in deriving cost metrics, leading to increased placement compile times and adverse impacts on the maximum frequency of design operation due to stale information and neglect of timing critical paths.
Innovation Solution
A hybrid hardware-software placement method that assigns components to either CAD tools or hardware placement units based on criteria, utilizing parallelism to compute cost metrics and address timing critical paths, allowing for efficient and accurate placement solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware assisted placement techniques are used to reduce placement compile time, then placement speed is improved, but the accuracy of cost metrics derivation deteriorates due to use of stale information
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing net boundary information before the placement process begins. This pre-computed data is then reused during hardware-assisted placement operations, eliminating the need to recalculate bounding box costs in real-time and preventing data staleness while maintaining high placement speed.
Solution Approach 2:
The patent changes the parameter representation by transforming net geometry information into boundary-based parameters (min_x, max_x, min_y, max_y) that can be efficiently stored and quickly retrieved. This parameter transformation enables accurate cost metric derivation without requiring complex real-time calculations.
2Productivity
If hardware assisted placement is used to increase parallelism, then placement compile time is reduced, but timing critical paths are neglected resulting in adverse impact on maximum frequency
Solution Approach 1:
The patent segments the placement optimization into two distinct phases: a hardware-assisted parallel phase that optimizes spatial arrangement using bounding box costs, and a subsequent timing analysis phase that identifies and optimizes critical paths. This segmentation allows both parallel processing efficiency and timing constraint satisfaction.
Solution Approach 2:
The patent implements feedback by using timing analysis results to guide subsequent placement iterations. The timing critical path information feeds back into the placement optimization process, allowing the system to adjust placements to satisfy timing constraints while maintaining the benefits of hardware-accelerated parallel processing.
3Manufacturing precision
If CAD tools are used for placement, then placement accuracy is maintained, but placement compile time increases significantly
Solution Approach 1:
The patent introduces an intermediary layer between CAD tools and the placement process: a hardware-assisted placement engine that uses pre-computed net boundary data. This intermediary enables fast parallel placement operations for non-critical components while maintaining the ability to invoke detailed CAD tool analysis when timing constraints require it, thus balancing speed and accuracy.
Data Source
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AI summary
A method for designing a system on a target device is disclosed. A first plurality of components in the system are assigned to be placed by an computer aided design (CAD) tool based on a criterion. A second plurality of components in the system are assigned to be placed by a hardware placement unit based on the criterion. Placement results from the CAD tool and the hardware placement unit are used to generate a placement solution for the system on the target device. Other embodiments are described and claimed.