Hybrid Fixed Programmable Header Parser for Network Devices
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Solution Overview
Problem
Network devices struggle with parsing headers of varying formats at wire speed due to the inflexibility of hardware engines and the high costs associated with programmable implementations.
Innovation Solution
A hybrid fixed/programmable header parser is introduced, comprising a fixed parsing circuit for known header types and a programmable parsing circuit with configurable circuitry and memory for parsing unknown or proprietary header types, allowing for efficient processing of both fixed and variable-length headers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hardware parsing engines are used for wire-speed processing, then processing speed is improved, but flexibility to support new header types deteriorates
Solution Approach 1:
The header parser is divided into two distinct segments: a fixed parsing circuit that handles known header types at wire speed, and a programmable parsing circuit that handles unknown or proprietary header types. This segmentation allows each component to specialize in its strengths, resolving the contradiction between speed and flexibility.
Solution Approach 2:
The programmable parsing circuit is designed to be reconfigurable, allowing it to adapt to different header formats and protocols. This multi-functionality enables the system to maintain wire-speed processing for common headers while also supporting new and proprietary header types without sacrificing speed.
2Adaptability or versatility
If programmable processors are used for header parsing, then flexibility to support new header types is improved, but processing speed deteriorates
Solution Approach 1:
By separating the parsing function into fixed and programmable segments, the system avoids using slow programmable processors for all header types. Instead, the fixed parsing circuit handles standard headers at wire speed, while the programmable circuit only intervenes when needed for unknown or proprietary formats.
Solution Approach 2:
The system applies different processing qualities to different parts of the header: wire-speed fixed processing for known, standardized header portions, and flexible programmable processing only for unknown or proprietary portions. This local differentiation optimizes overall performance.
3Adaptability or versatility
If fully programmable parsing is implemented, then support for proprietary header types is improved, but cost deteriorates
Solution Approach 1:
The parsing system is segmented into fixed and programmable components, allowing the expensive programmable portion to be minimized and only used when necessary. This reduces overall implementation cost compared to fully programmable solutions while maintaining support for proprietary headers.
Solution Approach 2:
The system uses a cost-effective fixed parsing circuit for the majority of common header types, reserving the more expensive programmable resources only for rare or proprietary cases. This asymmetric resource allocation reduces overall system cost.
Data Source
AI summary
A packet processor of a network device includes a forwarding engine that is configured to determine egress network interfaces via which packets received by the network device are to be transmitted. The packet processor also includes a header parser configured to parse header information in the packets received by the network device. The header parser includes a first parsing circuit that is configured to parse a first portion of a header of a packet and to prompt a programmable second parsing circuit to parse a second portion of the header. The first portion of the header has a header structure known to the first parsing circuit. The programmable second parsing circuit includes configurable circuitry and a memory to store control information that controls operation of the configurable circuitry to parse the second portion of the header.