Hybrid IC Assembly With 3D Interconnects for Thermal and Power Limits
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to optimize the performance of integrated circuit (IC) dies and packages by effectively communicating large numbers of signals between multiple dies in a multi-die IC package, which is constrained by thermal and power delivery limitations, especially as die sizes shrink.
Innovation Solution
The implementation of hybrid manufacturing techniques, where IC structures from different manufacturers, using different materials and techniques, are bonded together to form microelectronic assemblies with unique interconnect configurations and bonding materials, enabling efficient electrical connectivity and thermal management through the use of conductive vias and dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If die sizes are shrunk to increase density, then capacity increases, but thermal and power delivery limitations worsen
Solution Approach 1:
The patent divides the integrated circuit into multiple separate IC dies that are packaged individually and then interconnected within a single package. This segmentation allows each die to be optimized independently for thermal management while achieving high overall density through multi-die integration.
Solution Approach 2:
The patent transitions from planar 2D interconnection to 3D vertical interconnection by stacking multiple IC dies vertically and using through-silicon vias (TSVs) for inter-die connectivity. This dimensional change enables improved thermal pathways and power delivery while maintaining small footprint.
2Quantity of substance
If die sizes are shrunk to increase density, then capacity increases, but power delivery limitations worsen
Solution Approach 1:
Power delivery is segmented across multiple independent IC dies, each with its own power delivery network. This allows power to be distributed more efficiently through multiple parallel pathways via TSVs, reducing current density and improving overall power delivery capability despite smaller individual die sizes.
Solution Approach 2:
The patent implements vertical power delivery through TSVs that extend power pathways in the third dimension. This enables multiple power connections between dies, increasing total power delivery capacity while maintaining compact horizontal dimensions.
3Reliability
If multiple IC structures are bonded together, then electrical connectivity and thermal management improve, but manufacturing complexity increases
Solution Approach 1:
Each IC die is prepared in advance with pre-formed TSVs, bonding pads, and interconnect structures before packaging. This preliminary preparation of individual dies simplifies the final bonding process by reducing on-site manufacturing steps and enabling modular assembly of complex multi-die structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the ability to route power and signals between IC structures, reduces thermal constraints, and allows for more active circuitry in smaller IC structures, improving overall performance and capacity of microelectronic assemblies.
Implementation Method 1
a bonding material, bonding the second face of the first IC structure to the first face of the second IC structure
Implementation Method 2
an electrically conductive via having at least a portion in the first IC structure, at least a portion in the second IC structure, and extending through the bonding material
Data Source
AI summary
Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.