Hybrid IC Assembly Bonding for Thermal and Power Limits
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Solution Overview
Problem
The challenge in the semiconductor industry is to optimize the performance of integrated circuit (IC) dies and packages while addressing the complexities of communicating large numbers of signals between multiple dies due to size constraints, thermal issues, and power delivery limitations.
Innovation Solution
The implementation of hybrid manufacturing, which involves bonding IC structures fabricated by different manufacturers using various materials and techniques, to create microelectronic assemblies. These assemblies include interconnects with liners and electrically conductive fill materials, and may utilize different etch-stop materials and bonding configurations such as front-to-front, front-to-back, and back-to-back bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If IC features are scaled down to increase functional unit density, then capacity increases, but thermal issues and power delivery limitations worsen
Solution Approach 1:
The patent divides the IC package into multiple separate dies that are bonded together, rather than scaling down features on a single large die. This segmentation allows heat to be distributed across multiple smaller heat sources, improving thermal management while maintaining high functional unit density.
Solution Approach 2:
The patent transitions from horizontal scaling (shrinking features on a 2D plane) to vertical integration (stacking multiple dies in the third dimension). This 3D stacking approach increases capacity without proportionally increasing thermal density, as heat can dissipate through multiple surfaces and interfaces.
2Quantity of substance
If IC features are scaled down to increase functional unit density, then capacity increases, but power delivery limitations worsen
Solution Approach 1:
Power delivery is segmented across multiple independent dies, each with its own power distribution network. This allows power to be delivered more efficiently to smaller functional units without the cumulative resistance and voltage drop issues that plague scaled-down single-die architectures.
Solution Approach 2:
The patent uses vertical stacking to create short inter-die interconnect paths, reducing the horizontal distance over which power must be delivered. This 3D arrangement minimizes power loss while maintaining high functional density.
3Quantity of substance
If multiple dies are bonded together to increase capacity, then functional unit density increases, but device complexity increases
Solution Approach 1:
The patent employs universal bonding interfaces and standardized interconnect structures that can accommodate different die types and configurations. This modularity simplifies the bonding process and reduces complexity compared to custom-designed multi-die systems.
Solution Approach 2:
Die stacking and bonding are performed as preliminary actions during the manufacturing process, before final package assembly. This approach consolidates complexity into the fabrication stage rather than requiring complex assembly operations later, simplifying the overall device structure.
Data Source
AI summary
Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.