Hybrid IC Fault Simulation for Speed and Fault Coverage
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Solution Overview
Problem
Fault simulation in integrated circuits is computationally intensive and time-consuming, with serial fault simulation being slow and resource-demanding, while concurrent fault simulation, though faster, is complex and limited by hardware constraints.
Innovation Solution
A hybrid approach combining serial and concurrent fault simulation, where faults reaching limitations in concurrent simulation are switched to serial simulation, maintaining efficiency and accuracy by leveraging the strengths of both methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If serial fault simulation is used, then fault detection accuracy is improved, but computational time and resource consumption increase
Solution Approach 1:
The patent segments the fault simulation process into two distinct phases: a concurrent fault simulation phase for initial rapid testing, and a serial fault simulation phase for detailed accuracy verification. This segmentation allows the system to leverage the speed of concurrent simulation for bulk fault detection while reserving serial simulation for critical accuracy checks, thereby resolving the contradiction between speed and precision.
Solution Approach 2:
The patent applies partial serial simulation by selectively using serial fault simulation only for specific fault types or critical circuits where accuracy is paramount, rather than applying it universally to all faults. This partial application reduces overall computational time while maintaining high accuracy where needed, balancing the trade-off between speed and precision.
2Productivity
If concurrent fault simulation is used, then computational speed is improved, but system complexity and hardware requirements increase
Solution Approach 1:
The patent divides the simulation workload into two segments: concurrent simulation for high-speed processing of non-critical faults, and serial simulation for detailed analysis of critical faults. This segmentation allows the system to achieve high productivity for the majority of faults while keeping overall system complexity manageable by using simple serial simulation for edge cases.
Solution Approach 2:
The patent creates a universal fault simulation framework that can handle both concurrent and serial simulation modes within a single system architecture. The system dynamically selects the appropriate mode based on fault characteristics, making the system versatile and adaptable without requiring separate complex hardware configurations for different simulation types.
3Quantity of substance
If concurrent fault simulation is used, then resource consumption is reduced, but fault coverage and reliability are limited
Solution Approach 1:
The patent performs preliminary concurrent fault simulation to quickly identify and filter out obvious faults or non-critical failures. This preliminary action reduces the workload for subsequent serial simulation, allowing the system to maintain comprehensive fault coverage while reducing overall resource consumption by avoiding exhaustive serial simulation of all faults.
Solution Approach 2:
The patent applies partial serial simulation to critical fault types or high-risk circuits where comprehensive coverage is essential, while using concurrent simulation for the majority of non-critical faults. This partial application of resource-intensive serial simulation maintains high reliability for critical areas while reducing overall resource consumption.
Data Source
AI summary
Systems and methods for fault simulation are presented to reduce computation processing. A system includes a memory and a processor, operatively coupled to the memory, to perform fault simulation by injecting a plurality of faults into an IC model, initiating a concurrent fault simulation for all of the plurality of faults injected into the IC model, identifying at least one fault of the plurality of faults that is unable to be implemented by the concurrent fault simulation, and initiating a single fault simulation to process the at least one fault unable to be implemented by the concurrent fault simulation without interrupting the concurrent fault simulation from processing other faults of the plurality of faults. The at least one fault from the concurrent fault simulation is immediately discarded and the fault results from the concurrent fault simulation and the single fault simulation are combined upon completion of both simulations.