Hybrid Photonic-Electronic IC Assembly With 3D Via Interconnects

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Solution Overview

Problem

The integration of photonic and electronic components in microelectronic assemblies is challenging due to thermal constraints, power delivery limitations, and the complexity of communicating large numbers of signals between dies in multi-die IC packages, which hinders the optimization of IC performance and the incorporation of fast and efficient photonics-based technologies.

Innovation Solution

Hybrid manufacturing techniques are employed to bond IC structures with different materials and manufacturing methods, integrating photonic components like optical waveguides and electronic components such as interconnects, allowing for the creation of microelectronic assemblies with electrically conductive vias and waveguides that provide optical interconnections and improved connectivity between IC structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If photonic and electronic components are integrated in multi-die IC packages, then functional capacity and communication efficiency are improved, but thermal constraints and power delivery limitations worsen

Engineering Contradiction:
Improvecommunication efficiencyVSAvoidthermal constraints
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The patent divides the integrated circuit into multiple separate dies, with photonic components on one die and electronic components on another die. This segmentation allows independent thermal management and power delivery optimization for each component type, resolving the thermal and power delivery constraints that would arise from integrating both types in a single die.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a substrate as an intermediary between photonic and electronic dies. The substrate provides separate thermal pathways and power delivery networks, allowing heat from photonic components to be dissipated independently from electronic components, while also providing dedicated power delivery routes that prevent power delivery limitations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If the number of signal communication paths between dies is increased, then data transmission capacity is improved, but manufacturing complexity and interconnect resistance worsen

Engineering Contradiction:
Improvesignal communication pathsVSAvoidinterconnect complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent transitions from planar interconnect routing to three-dimensional vertical routing through substrate through-holes. This dimensional change allows multiple signal paths to be stacked vertically, increasing communication capacity without proportionally increasing lateral interconnect complexity. The substrate through-holes provide direct vertical pathways that simplify the overall interconnect architecture.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent forms conductive plugs and through-holes in the substrate before bonding the photonic and electronic dies. This preliminary action creates pre-established low-resistance electrical pathways that simplify subsequent assembly and reduce overall interconnect resistance, avoiding the need to create these complex pathways after die bonding.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If hybrid manufacturing techniques are used to bond IC structures with different materials, then manufacturing flexibility and component integration are improved, but manufacturing precision and process control worsen

Engineering Contradiction:
Improvemanufacturing flexibilityVSAvoidbonding precision
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent applies different material properties and bonding approaches to different regions of the substrate. The substrate is designed with localized conductive regions for electrical interconnects and non-conductive regions for optical waveguides. This local differentiation allows precise control over bonding characteristics in each region, maintaining manufacturing precision while enabling hybrid manufacturing flexibility.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent modifies substrate parameters (conductivity, refractive index, mechanical properties) in different regions to optimize bonding precision. By changing material parameters locally, the substrate can provide precise alignment features, controlled thermal expansion, and optimized bonding surface properties, thereby maintaining high manufacturing precision despite using diverse photonic and electronic components.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12147083B2Hybrid manufacturing for integrating photonic and electronic components
Publication Date: 2024.11.19 INTEL CORP
  • US12147083B2 patent drawing
  • US12147083B2 patent drawing
  • US12147083B2 patent drawing

AI summary

Microelectronic assemblies fabricated using hybrid manufacturing for integrating photonic and electronic components, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by bonding at least two IC structures fabricated using different manufacturers, materials, or manufacturing techniques. Before bonding, at least one IC structure may include photonic components such as optical waveguides, electro-optic modulators, and monolithically integrated lenses, and at least one may include electronic components such as electrically conductive interconnects, transistors, and resistors. One or more additional electronic and/or photonic components may be provided in one or more of these IC structures after bonding. For example, an interconnect implemented as an electrically conductive via or a waveguide implemented as a dielectric via may be provided after bonding to extend through one or more of the bonded IC structures.