Hybrid Planar-Trench IGBT Layout for Low Loss and Blocking
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Solution Overview
Problem
Existing power semiconductor devices face challenges with high on-state losses, significant hole drainage, unstable gate parameters, reduced blocking capability, and high switching losses due to complex design requirements and alignment processes.
Innovation Solution
A planar Insulated Gate Bipolar Transistor (IGBT) design that integrates trench and planar MOS cell concepts, featuring a lateral/horizontal channel and orthogonal trenches, which allows for reduced hole drainage, stable gate parameters, improved blocking capability, and lower on-state losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If trench cell design is used to reduce conduction losses and improve carrier enhancement, then on-state losses are reduced, but blocking capability deteriorates due to high peak electric fields at trench corners
Solution Approach 1:
The device segments the cell structure into planar regions and trench regions, with planar gates forming lateral channels in mesa regions and trench gates forming vertical channels in trench regions. This segmentation allows each region to contribute its strengths: planar regions provide low peak fields for good blocking, while trench regions provide high carrier enhancement for low conduction losses.
Solution Approach 2:
Different regions of the device are given different structures and properties: planar mesa regions have lateral channels with good blocking characteristics, while trench regions have vertical channels with high carrier enhancement. The gate structure, channel formation, and doping profiles are locally optimized for each region's specific function.
2Reliability
If planar cell design is used to provide good blocking capability and controllability, then reliability is improved, but conduction losses increase due to non-optimal charge spreading and lateral channel limitations
Solution Approach 1:
The invention merges planar and trench cell concepts into a hybrid structure where both planar lateral channels and trench vertical channels coexist and contribute to device operation. The planar gate structure provides good blocking and controllability, while the integrated trench structure adds vertical channel benefits for improved carrier enhancement and reduced conduction losses.
3Manufacturing precision
If complex alignment processes are used to achieve precise trench positioning, then manufacturing precision is improved, but device complexity and production difficulty increase
Solution Approach 1:
The planar gate structure and its associated layers are formed first, establishing a well-defined reference framework. The trench structure is then formed in relation to this pre-established planar structure, using it as an alignment reference. This preliminary action simplifies subsequent alignment processes compared to forming both structures simultaneously or forming trenches first without a reference framework.
Data Source
AI summary
A Metal Oxide Semiconductor (MOS) cell design has traditional planar cells extending in a first dimension, and trenches with their length extending in a third dimension, orthogonal to the first dimension in a top view. The manufacturing process includes forming a horizontal channel, and a plurality of trenches discontinued in the planar cell regions. Horizontal planar channels are formed in the mesa of the orthogonal trenches. A series connected horizontal planar channel and a vertical trench channel are formed along the trench regions surrounded by the first base. The lack of a traditional vertical channel is important to avoid significant reliability issues (shifts in threshold voltage Vth). The planar cell design offers a range of advantages both in terms of performance and processability. Manufacture of the planar cell is based on a self-aligned process with minimum number of masks, with the potential of applying additional layers or structures.