Hybrid Image Sensor Manufacturing on Glass Substrates
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Solution Overview
Problem
The high manufacturing costs of image sensor devices, particularly those on glass or plastic substrates, due to the use of traditional semiconductor materials and processes, and the difficulty in combining these with organic materials and processes.
Innovation Solution
A method for manufacturing image sensor devices on glass substrates using a series of layers including a metalized thin film transistor layer, inter-layer dielectric layers, metal layers, bank layers, electron transport layers, bulk heterojunction layers, hole transport layers, and top contact layers, employing organic materials and processes that are compatible with traditional semiconductor methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional semiconductor materials and processes are used to manufacture image sensor devices on glass substrates, then manufacturing precision and device performance are maintained, but manufacturing costs increase significantly
Solution Approach 1:
The patent employs a hybrid manufacturing approach that combines traditional semiconductor materials (such as metalized thin film transistor layers, inter-layer dielectric layers, and metal contact layers) with organic materials (such as electron transport layers, bulk heterojunction layers, and hole transport layers). This composite material strategy allows the device to maintain the high precision and performance characteristics of semiconductor manufacturing while incorporating cost-effective organic materials that can be processed using simpler, lower-cost techniques.
2Ease of manufacture
If organic materials are used to reduce manufacturing costs, then manufacturing cost decreases, but compatibility with traditional semiconductor manufacturing methods becomes difficult
Solution Approach 1:
The patent divides the image sensor device into distinct functional layers, with traditional semiconductor materials used for the lower layers (thin film transistor layer, inter-layer dielectric layers, metal contact layers) and organic materials used for the upper functional layers (electron transport layer, bulk heterojunction layer, hole transport layer, top contact layer). This segmentation allows each material system to be optimized independently, enabling cost-effective organic materials to be integrated without compromising the precision of semiconductor manufacturing processes.
Solution Approach 2:
The patent introduces intermediate layers and structures that facilitate the integration between traditional semiconductor materials and organic materials. These intermediary elements serve as transition zones that ensure proper electrical contact, mechanical adhesion, and process compatibility between the two different material systems, thereby enabling the combination of low-cost organic materials with precise semiconductor manufacturing methods.
3Reliability
If multiple layers are combined to achieve both cost reduction and performance, then device functionality is improved, but device complexity increases
Solution Approach 1:
The patent designs the multi-layer structure so that each layer serves multiple functions. For example, the metalized thin film transistor layer provides both electrical conduction and structural support, while the inter-layer dielectric layers provide both electrical insulation and mechanical planarization. The organic layers (electron transport, bulk heterojunction, hole transport) collectively provide photoelectric conversion, charge separation, and charge transport functions. This multi-functionality approach reduces the need for additional specialized layers, thereby managing device complexity while maintaining enhanced functionality.
Data Source
AI summary
A method of manufacturing an image sensor device includes providing a metalized thin film transistor layer on a glass substrate; forming an inter-layer dielectric layer on the metalized thin film transistor layer; forming a via through the inter-layer dielectric layer; forming a metal layer the inter-layer dielectric and within the inter-layer dielectric layer via for contacting the metalized thin film transistor layer; forming a bank layer on the metal layer and the inter-layer dielectric layer; forming a via through the bank layer; forming an electron transport layer on the bank layer and within the bank layer via for contacting an upper surface of the metal layer; forming a bulk heterojunction layer on the electron transport layer; forming a hole transport layer on the bulk heterojunction layer; and forming a top contact layer on the hole transport layer.