Hybrid Integrator Circuit With Buffer Delay Chain for Continuous Conversion
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Solution Overview
Problem
Existing hybrid integrators face challenges in continuous integration, accuracy, power consumption, and time delay due to mismatches between quantizers and feedback capacitors, and limitations in storing both digital and analog signals simultaneously.
Innovation Solution
A hybrid integrator design featuring an operational amplifier, capacitors, and buffers forming a delay chain, which allows for simultaneous integration and digital conversion of input signals, reducing power consumption and eliminating mismatches, enabling continuous integration with minimal time delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an analog operational amplifier is used for integration, then high gain and noise shaping are achieved, but high static power is consumed
Solution Approach 1:
The patent segments the integration function into two parts: a low-power switched-capacitor integrator for the main integration operation, and a separate digital filter for post-processing. This segmentation allows the analog operational amplifier to be replaced with a lower-power switched-capacitor structure while maintaining integration accuracy through the digital filter compensation.
Solution Approach 2:
The patent replaces the continuous analog operational amplifier-based integration mechanism with a discrete switched-capacitor integration mechanism. This substitution uses timing-controlled switch operations instead of continuous analog amplification, dramatically reducing static power consumption while achieving equivalent or superior integration performance through digital filtering.
2Use of energy by moving object
If a digital integrator is used, then power consumption is reduced, but storable accuracy is limited and errors accumulate
Solution Approach 1:
The patent merges the switched-capacitor integrator (providing low-power analog-like integration) with a digital filter (providing error correction and precision enhancement). This combination allows the system to benefit from both the low power consumption of digital circuits and the high accuracy of analog integration, with the digital filter compensating for quantization errors and preventing error accumulation.
3Adaptability or versatility
If quantization is performed before integration, then digital signal processing is enabled, but time delay is introduced and continuous integration is prevented
Solution Approach 1:
The patent performs preliminary integration using the switched-capacitor integrator before digital quantization and filtering. This preliminary action allows the integration operation to occur in the analog domain without quantization-induced delay, and the digital processing is applied afterward to enable versatile digital signal processing while maintaining continuous integration capability.
4Measurement precision
If additional quantizers are added to improve accuracy, then measurement precision is enhanced, but device complexity increases
Solution Approach 1:
The patent uses a single quantizer to create a digital representation of the integrated signal, then uses digital filtering and processing to achieve the equivalent of multiple quantization stages. This copying approach allows high precision to be achieved through software/digital processing rather than adding multiple hardware quantizer stages, significantly reducing circuit complexity while maintaining or improving measurement precision.
Data Source
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AI summary
The present disclosure provides an analog-digital hybrid integrator circuit which includes an operational amplifier coupled to an input terminal, a first capacitor coupled to the input terminal in parallel with the operational amplifier, a plurality of second capacitors coupled in parallel with the first capacitor, and a plurality of buffers that is coupled in series and is coupled in parallel with the plurality of second capacitors, respectively.