Hybrid Integrator Circuit With Circular Delay Chains for Linearity
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Solution Overview
Problem
Existing hybrid integrators face challenges in continuous integration, suffer from time delays, and exhibit nonlinearity due to mismatches between quantizers and feedback capacitors, limiting their performance in analog-to-digital conversion.
Innovation Solution
A hybrid integrator design that incorporates an operational amplifier, capacitors, and a series-parallel buffer configuration to enable simultaneous integration and digital conversion, reducing power consumption and eliminating the need for additional quantizers, while maintaining high linearity and speed through circular delay chains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If an analog operational amplifier is used for integration, then high gain and continuous integration are achieved, but high static power consumption occurs
Solution Approach 1:
The patent segments the integration function into two parts: a low-power digital integrator for the main integration task and a separate analog residual signal path for high-precision correction. This segmentation allows the digital portion to consume minimal power while the analog portion handles only the residual error signal, significantly reducing overall power consumption compared to using a full analog operational amplifier.
Solution Approach 2:
The patent merges digital and analog domains into a hybrid architecture where digital quantized signals and analog residual signals are combined through feedback capacitors. This merging allows the system to leverage the low power consumption of digital circuits while maintaining the high precision and continuous integration capability of analog circuits.
2Use of energy by moving object
If a digital integrator is used for integration, then low power consumption is achieved, but quantization error and limited storable accuracy occur
Solution Approach 1:
The patent introduces an analog residual signal as an intermediary element that carries the quantization error from the digital domain back to the analog domain. This residual signal acts as a mediator that compensates for the quantization error, allowing the digital integrator to maintain low power consumption while the analog residual path restores the lost precision.
Solution Approach 2:
The patent implements a feedback mechanism where the analog residual signal is fed back through capacitors to the input of the digital integrator. This feedback loop continuously corrects the quantization error by reintroducing the discarded analog information, thereby improving overall integration accuracy without significantly increasing power consumption.
3Adaptability or versatility
If quantization is performed before integration in hybrid integrators, then digital signal processing is enabled, but time delay and nonlinearity due to mismatch occur
Solution Approach 1:
The patent performs preliminary digital quantization of the input signal before the integration process begins. By pre-quantizing the signal and preparing the digital code, the system eliminates the need for time-consuming analog-to-digital conversion during the integration process itself, thereby reducing time delay while maintaining digital signal processing capabilities.
Data Source
AI summary
The present disclosure provides an analog-digital hybrid integrator circuit which includes an operational amplifier coupled to an input terminal, a first capacitor coupled to the input terminal in parallel with the operational amplifier, a plurality of second capacitors coupled in parallel with the first capacitor, and a plurality of buffers that is coupled in series and is coupled in parallel with the plurality of second capacitors, respectively.