Hybrid Interconnect Architecture for 3D Processing Systems
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Solution Overview
Problem
Conventional three-dimensional processing systems face limitations in efficiency and performance due to the need for power and bandwidth overhead when allowing all processor cores to access all memory elements, which reduces the benefits of localized communication within vertical columns of memory partitions.
Innovation Solution
A hybrid interconnect system providing two independent memory access paths – a global memory access path for all partitions and local memory access paths for specific subsets of processor cores, allowing selective access based on physical addresses, operation types, and data content, thereby minimizing horizontal wire traversal and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all processor cores can access all memory elements, then system adaptability and versatility are improved, but power consumption and bandwidth overhead increase
Solution Approach 1:
The patent segments memory access paths into local and global paths. Local paths connect processor cores to vertically-aligned memory partitions, while global paths provide universal access. This segmentation allows the system to use low-power local paths for most accesses while reserving global paths for cross-vault communications, resolving the contradiction between accessibility and power consumption.
Solution Approach 2:
The patent implements local memory access paths that provide specialized high-performance access for locally-aligned memory partitions. These local paths have different characteristics (lower power, dedicated bandwidth) compared to global paths, allowing the system to optimize for local accesses while maintaining global accessibility when needed.
2Adaptability or versatility
If all processor cores can access all memory elements, then system adaptability and versatility are improved, but bandwidth overhead increases
Solution Approach 1:
The patent divides the memory access infrastructure into separate local and global pathways. Local paths handle traffic for vertically-aligned memory partitions, while global paths handle inter-vault communications. This segmentation reduces the bandwidth burden on any single path and eliminates the need for high-capacity global interconnects to serve all accesses.
3Use of energy by moving object
If localized communication within vertical columns is implemented, then power and bandwidth overhead are reduced, but device complexity increases
Solution Approach 1:
The patent designs the interconnect structure so that global memory access paths serve multiple functions: they provide access to all memory partitions when needed, and can be selectively activated based on access patterns. This multi-functionality reduces the need for completely separate infrastructure for local and global access, thereby limiting complexity growth.
4Loss of energy
If localized communication within vertical columns is implemented, then power and bandwidth overhead are reduced, but hardware complexity increases
Solution Approach 1:
The patent implements dynamic selection between local and global memory access paths based on the memory access request characteristics. The system can adaptively route accesses to minimize energy consumption while maintaining performance, allowing the architecture to optimize its complexity usage based on workload patterns rather than providing static complex infrastructure.
Data Source
AI summary
A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.