Hybrid Interconnect Layout for Mixed-Width Low-Resistance Metal Lines
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Solution Overview
Problem
Conventional semiconductor structures face challenges in forming narrow and wide interconnect lines with optimal resistance and material utilization, particularly when using non-Cu conductors like Ru/Co, which result in high resistance for wide lines and limited performance.
Innovation Solution
The integration of hybrid damascene and subtractive etch processing is used to form narrow lines with non-Cu materials (e.g., Ru/Co) and wide lines with Cu within the same metal level, optimizing resistance by creating distinct taper angles and via configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If non-Cu materials (Ru/Co) are used for wide interconnect lines, then manufacturing process is simplified, but line resistance increases significantly
Solution Approach 1:
The patent applies local quality by using different materials for different line widths within the same interconnect level. Non-Cu materials (Ru/Co) are used for narrow lines where they provide adequate resistance characteristics, while Cu materials are used for wide lines where low resistance is critical. This localized material selection optimizes both manufacturing simplicity and electrical performance across different regions of the interconnect structure.
Solution Approach 2:
The patent segments the interconnect lines into two categories based on width: narrow lines and wide lines. This segmentation allows the application of different material systems optimized for each type. The segmentation is implemented through separate patterning and filling processes that target specific line width ranges, enabling independent optimization of material properties for each segment type.
2Reliability
If Cu material is used for wide interconnect lines, then line resistance is minimized, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into separate flow paths for narrow and wide lines. Wide lines undergo Cu-filled damascene processing while narrow lines use non-Cu material deposition. This segmentation of the manufacturing process allows each line type to receive specialized treatment optimized for its electrical requirements without unnecessarily complicating the overall process for all lines.
Solution Approach 2:
The patent implements local quality in the manufacturing process by applying different material deposition and filling techniques to different regions. Cu-based processes are applied locally to wide line regions where low resistance is paramount, while simpler non-Cu processes are applied to narrow line regions. This localized manufacturing approach minimizes overall process complexity while achieving optimal resistance characteristics where needed.
3Ease of manufacture
If all interconnect lines are formed with the same material, then manufacturing process is simplified, but performance is limited for both narrow and wide lines
Solution Approach 1:
The patent implements local quality by selecting materials based on the specific performance requirements of each line width category. Non-Cu materials provide adequate resistance for narrow lines while Cu materials provide optimal resistance for wide lines. This localized material optimization significantly improves overall device performance compared to using a single material system for all lines, while the differential processing flows are designed to maintain reasonable manufacturing simplicity.
Solution Approach 2:
The patent effectively creates a composite interconnect structure at the system level, combining different material systems (non-Cu and Cu) within the same interconnect level. This composite approach allows the interconnect network to leverage the advantages of each material type in appropriate locations, achieving superior overall performance that neither material could provide alone when used universally.
Data Source
AI summary
A semiconductor structure comprises two or more interconnect lines of a first width in a given interconnect level, and two or more interconnect lines of a second width in the given interconnect level. The two or more interconnect lines of the second width are disposed between a first one of the two or more interconnect lines of the first width and a second one of the two or more interconnect lines of the second width. The two or more interconnect lines of the first width have sidewalls with a negative taper angle. The two or more interconnect lines of the second width have sidewalls with a positive taper angle.