Hybrid Serial-Parallel Interface for Low-Power Data Links

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Solution Overview

Problem

Conventional serial interfaces, such as CDR-based interfaces, consume significant power due to the CDR circuit and reference oscillator, especially at high frequencies, and switching to low power modes results in unacceptable startup latency and power wastage.

Innovation Solution

A hybrid interface that dynamically switches between serial and parallel communication modes, sharing pins and eliminating the CDR component, thereby reducing power consumption and latency by utilizing a parallel interface with negligible startup latency and no reference oscillator.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a CDR-based serial interface is used, then high-frequency data transmission is achieved, but power consumption increases significantly

Engineering Contradiction:
Improvedata transmission frequencyVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The interface dynamically switches between serial mode (for high-frequency transmission) and parallel mode (for low-frequency transmission), adapting the communication protocol to the current data rate requirements. This dynamic adaptation allows the system to use the power-efficient parallel mode during low-speed operations while maintaining the capability for high-speed serial communication when needed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent extracts and removes the CDR circuit and reference oscillator from the interface architecture. By eliminating these power-consuming components entirely and using a simplified parallel interface for low-speed communication, the system achieves significant power savings without requiring the complex clock recovery mechanisms needed in traditional serial interfaces.

Inventive Principle:
Principle #2Taking out (Extraction)

2Use of energy by moving object

If the interface is switched off to reduce power consumption, then power savings are achieved, but startup latency becomes unacceptable

Engineering Contradiction:
Improvepower consumptionVSAvoidstartup latency
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The parallel interface is designed to be immediately available and operational without requiring preliminary initialization of complex clock recovery circuits. Since the parallel mode does not depend on CDR or reference oscillator startup, the system can transition to operational state instantly when needed, eliminating the startup latency problem.

Inventive Principle:
Principle #10Preliminary action

3Use of energy by moving object

If low power mode is implemented by running circuitry at lower frequencies, then some power savings are achieved, but significant power reduction is not realized

Engineering Contradiction:
Improvepower consumptionVSAvoiddata transmission efficiency
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The system dynamically selects between serial and parallel communication modes based on the required data transmission rate. For low-speed applications, the parallel mode provides sufficient bandwidth while consuming minimal power, and for high-speed requirements, the serial mode delivers the necessary throughput. This dynamic mode selection optimizes both power efficiency and transmission efficiency for different operating conditions.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20110196997A1Hybrid interface for serial and parallel communication
Publication Date: 2011.08.11 LATTICE SEMICON CORP
  • US20110196997A1 patent drawing
  • US20110196997A1 patent drawing
  • US20110196997A1 patent drawing

AI summary

Embodiments of the invention are generally directed to a hybrid interface for serial and parallel communication. An embodiment of a method includes initializing a first apparatus for transmission of data to or reception of data from a second apparatus, switching an interface for the first apparatus to a first mode for a parallel interface, the parallel interface including a first plurality of pins, and transmitting or receiving parallel data in the first mode via the first plurality of pins. The method further includes switching the interface of the first apparatus to a second mode for a serial interface, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, and transmitting or receiving serial data in the second mode via the second plurality of pins.