Hybrid-Bonded Interposer Cores for 3D Memory Bandwidth Bottlenecks
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Solution Overview
Problem
Multi-die or multi-chiplet computing systems face memory deficiencies and bottlenecks, particularly in high-performance computing systems, which are not adequately addressed by traditional 2.5D packaging or vertical stacking techniques using typical core substrates and redistribution layer interposers.
Innovation Solution
The development of core substrates with embedded components, allowing for both the mounting of components on one side and embedding of components within the substrate, which includes active components like HBM and passive components such as trench capacitors, transistors, and liquid cooling channels, using silicon substrates with matched thermal expansion coefficients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 2.5D packaging or vertical stacking techniques are used, then device integration is achieved, but memory capacity and bandwidth are insufficient
Solution Approach 1:
The patent transitions from traditional 2.5D packaging to true 3D stacking by embedding memory components within the substrate volume rather than only on surfaces. Multiple memory dies are stacked vertically and interconnected through through-substrate vias, utilizing the third dimension to dramatically increase memory capacity and bandwidth while reducing the memory resource bottleneck that limits traditional approaches
2Quantity of substance
If components are embedded within the substrate, then memory capacity increases, but manufacturing complexity increases
Solution Approach 1:
The patent divides the memory system into discrete modular components including multiple memory dies, interposer substrates, and redistribution layers that can be independently fabricated and then assembled through hybrid bonding. This segmentation allows each component to be optimized separately while maintaining overall system integration, reducing the manufacturing complexity compared to monolithic 3D integration
Solution Approach 2:
The patent introduces an interposer substrate as an intermediary component that facilitates the integration of memory dies with processor chips. The interposer provides redistribution layers and hybrid bonding interfaces that simplify the connection between different memory stacks and processing units, making the overall manufacturing process more manageable despite the increased integration density
3Productivity
If multiple memory dies are stacked vertically, then memory bandwidth improves, but thermal management becomes more difficult
Solution Approach 1:
The interposer substrate acts as a thermal intermediary between the vertically stacked memory dies and the external environment. It provides thermal pathways and interfaces for heat dissipation while maintaining the high-density vertical stacking configuration that enables improved memory bandwidth
Data Source
AI summary
An interposer device includes a first core, a second core hybrid bonded to the first core, a first redistribution layer (RDL), and a second RDL. The first core and the second core are located between the first RDL and the second RDL.