Hybrid Interposer Embedding Passive Components for Signal Path Reduction
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in reducing signal path length and increasing area while reducing costs, particularly in high bandwidth memory (HBM) applications, where silicon interposers are costly and difficult to manufacture, and organic interposers can suffer from warpage and thermal expansion issues.
Innovation Solution
A hybrid interposer with a core substrate having cavities for embedded passive components, connected via through-vias and insulating layers, and a redistribution layer for efficient electrical connection, allowing passive components to be placed adjacent to semiconductor chips, thereby reducing signal path length and improving rigidity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon interposer is used, then manufacturing precision and reliability are improved, but manufacturing cost increases
Solution Approach 1:
The patent uses a composite structure combining organic substrate material with embedded passive components and through-vias. This composite approach achieves the mechanical strength and electrical performance of silicon interposers while using lower-cost organic materials, directly resolving the contradiction between reliability and manufacturing cost.
2Ease of manufacture
If organic interposer is used, then manufacturing cost is reduced, but warpage and thermal expansion issues occur
Solution Approach 1:
The patent applies local quality enhancement by strategically embedding passive components and through-vias in specific regions of the organic substrate. This localized reinforcement compensates for the inherent weaknesses of organic materials regarding warpage and thermal expansion, maintaining structural stability while keeping costs low.
Solution Approach 2:
The organic substrate is combined with passive components and conductive through-vias to create a composite structure that enhances dimensional stability and reduces warpage, while maintaining the cost advantages of organic materials.
3Length of moving object
If passive components are disposed adjacent to semiconductor chip, then signal path length is reduced, but device complexity increases
Solution Approach 1:
The patent merges the passive components directly into the interposer substrate through embedding, combining multiple functions (interposition, signal routing, and passive component hosting) into a single integrated structure. This reduces signal path length while avoiding the complexity of separate component assemblies.
Solution Approach 2:
Passive components are nested within cavities formed in the interposer substrate, with through-vias providing electrical connections. This nesting approach consolidates multiple elements into a compact integrated structure, reducing overall package complexity while achieving short signal paths.
4Productivity
If interposer area is increased, then productivity and bandwidth are improved, but manufacturing difficulty increases
Solution Approach 1:
The patent segments the interposer into a modular organic substrate structure with standardized through-via patterns and passive component placements. This segmentation enables scalable manufacturing of larger area interposers while maintaining process simplicity, thus improving bandwidth without proportionally increasing manufacturing difficulty.
Data Source
AI summary
A method of manufacturing a semiconductor package includes preparing a core substrate having an upper surface and a lower surface, and including a cavity. A passive component is disposed in the cavity. A first insulating layer is formed on the upper surface of the core substrate and in the cavity and encapsulates the passive component. Through-vias are formed that penetrate the core substrate and the first insulating layer, and a first wiring layer is formed on the first insulating layer. The first wiring layer connects the through-vias and the passive component. A connection structure including an insulating member is formed on the first insulating layer and a redistribution layer is formed in the insulating member. The redistribution layer is connected to the first wiring layer. A semiconductor chip is disposed on an upper surface of the connection structure. The semiconductor chip has connection pads connected to the redistribution layer.