Hybrid Interposer Embedding Devices via Stress Buffering
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Solution Overview
Problem
Conventional silicon interposers face challenges in embedding integrated devices due to high processing temperatures, which can damage susceptible devices and limit the variety of integrated devices that can be used, leading to manufacturing defects and reduced processing speed.
Innovation Solution
A hybrid interposer structure is introduced, comprising a non-organic material layer, an organic material layer with low Young's modulus, and a molding structure with higher Young's modulus, which acts as a stress buffer and buffer between heterogeneous layers, allowing for the embedding of a wider variety of integrated devices closer to semiconductor dies and reducing manufacturing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high processing temperatures are used to form silicon interposer, then electrical signal communication between semiconductor dies and PCB is achieved, but integrated devices are damaged and manufacturing defects increase
Solution Approach 1:
The patent introduces a hybrid interposer structure comprising an organic material layer and a non-organic material layer. The organic material layer serves as a protective intermediary that buffers thermal stress and protects integrated devices from damage during high-temperature processing, while the non-organic material layer provides the necessary electrical signal communication pathways. This layered intermediary structure resolves the contradiction by allowing high-temperature processing to occur while protecting susceptible integrated devices.
Solution Approach 2:
The patent employs a composite hybrid interposer structure combining organic and non-organic materials. The organic material layer (e.g., polyimide) provides thermal buffering and mechanical flexibility, while the non-organic material layer (e.g., silicon dioxide or silicon nitride) provides electrical insulation and structural stability. This composite material approach enables the system to withstand high processing temperatures without damaging integrated devices, while maintaining electrical signal communication functionality.
2Reliability
If conventional silicon interposer is used, then electrical communication is established, but the variety of integrated devices that can be embedded is limited
Solution Approach 1:
The patent changes the material parameters of the interposer by introducing an organic material layer with specific thermal and mechanical properties (e.g., lower thermal expansion coefficient, lower Young's modulus). This parameter change creates a more favorable processing environment that accommodates a wider variety of integrated devices with different thermal and mechanical characteristics, while maintaining electrical communication functionality through the non-organic material layer.
3Productivity
If integrated devices are embedded closer to semiconductor dies, then processing speed increases, but manufacturing defects increase due to high temperature exposure
Solution Approach 1:
The patent applies beforehand cushioning by placing the organic material layer between the integrated devices and the high-temperature processing environment. This protective layer is positioned in advance to cushion and absorb thermal stress during subsequent high-temperature processing steps, enabling integrated devices to be embedded closer to semiconductor dies for faster processing without suffering temperature-induced damage or manufacturing defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hybrid interposer enhances electrical performance, structural integrity, and reduces the physical length of electrical communication pathways, thereby increasing processing speed and reducing the likelihood of hardware errors and manufacturing defects.
Implementation Method 1
an organic material layer with low Young's modulus, and a molding structure with higher Young's modulus, which acts as a stress buffer and buffer between heterogeneous layers
Implementation Method 2
a molding structure with higher Young's modulus, which acts as a stress buffer and buffer between heterogeneous layers
Data Source
AI summary
Devices and methods of manufacture for a hybrid interposer including a molding structure within a semiconductor device. A semiconductor device may include a semiconductor die, a package substrate, and a hybrid interposer positioned between the semiconductor die and the package substrate. The hybrid interposer may include a molding material layer, and an integrated device positioned within the molding interposer layer. The hybrid interposer may further include an organic material layer, and a non-organic material layer. The molding material layer may include an epoxy molding compound (EMC). The organic material layer may include a dielectric polymer material. The non-organic material layer may include a silicon-based dielectric material.


