Hybrid Lane Stalling Bus Architecture for Power and EMI Reduction
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Solution Overview
Problem
As computing systems become more complex, their interconnect architectures face challenges in balancing high performance with power efficiency, particularly in meeting diverse market demands such as servers and mobile devices, where energy conservation and reduced electromagnetic interference (EMI) are crucial.
Innovation Solution
The implementation of a hybrid lane stalling data link architecture, where a master lane maintains activity during inactivity to synchronize non-master lanes, reducing power consumption and EMI by minimizing unnecessary signaling, and the use of no-lock bus architectures with multiple bit redundancy and voting to recover clock and determine logic states without high-speed synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If continuous synchronization is used to maintain data integrity across lanes, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic synchronization only when needed by using idle characters inserted at specific intervals (e.g., every 256 characters) rather than continuous synchronization. The receiver detects these idle characters and performs synchronization only at these periodic intervals, reducing power consumption while maintaining data integrity.
Solution Approach 2:
The patent extracts the synchronization function from continuous operation and separates it into discrete, event-driven operations triggered only by detected idle characters. This allows the system to maintain reliability through synchronization while eliminating unnecessary power consumption during data transmission periods.
2Reliability
If all lanes remain active during idle periods to maintain synchronization, then reliability is improved, but electromagnetic interference increases
Solution Approach 1:
The patent uses periodic idle character insertion to trigger synchronization only when needed, allowing lanes to remain in a low-power, low-EMI state during idle periods. The receiver wakes up periodically to detect idle characters and perform synchronization, rather than maintaining continuous active signaling.
Solution Approach 2:
The patent applies different operational states to different lanes based on local conditions - active lanes transmit data while idle lanes remain dormant. The master lane maintains periodic activity to trigger synchronization, while slave lanes remain inactive until needed, reducing overall EMI while maintaining synchronization capability.
3Adaptability or versatility
If wake-up protocols are implemented for idle lanes, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent merges the wake-up protocol with the existing idle character mechanism already used for synchronization. The same idle characters that trigger synchronization in the receiver also serve as wake-up signals for idle lanes, eliminating the need for separate wake-up protocols and reducing overall system complexity.
Solution Approach 2:
The idle character serves multiple functions simultaneously: it acts as a synchronization trigger for the receiver, a wake-up signal for idle lanes, and a flow control mechanism. This multi-functionality reduces the need for separate protocols and simplifies the overall system architecture.
4Productivity
If fill characters are transmitted during idle periods to maintain activity, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent transmits fill characters periodically at controlled intervals rather than continuously filling idle lanes. The master lane inserts idle characters at specific rates (e.g., one idle character every N data characters), allowing lanes to remain inactive during true idle periods while maintaining periodic availability, thus reducing power consumption while preserving productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces power consumption and EMI by minimizing idle lane activity and eliminating the need for continuous synchronization, thereby enhancing both performance and energy efficiency across various computing platforms.
Implementation Method 1
a data-rate phase-locked loop, PLL, arranged to lock the clock recovery for all non-master lanes to the master lane
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
A method, apparatus, and system to recover a clock for a bus comprising: to assign a master lane, to lock non-master lanes to the master lane, to fill the master lane during data inactivity, to idle the non-master lanes during data inactivity, to maintain clock for the master lane, and to recover the clock for the non-master lanes from the master lane. A method, apparatus, and system to transmit and receive serial data with an unsynchronized clock comprising: to transmit data in a bit stream, the data have multiple bit redundancy, to receive the data in the bit stream, to sample a value of the data in the bit stream, to use voting on the value of the data in the bit stream, and to determine a correct logic state for the data from the voting.