Hybrid Data Latch Switching Between Pulse and Two-Stage Modes
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Solution Overview
Problem
Existing data storage circuits in processors face challenges in operating efficiently across a wide range of power supply voltage levels and frequencies, particularly in battery-powered devices, as they either consume excess power or perform poorly in reduced power modes, and designing circuits for wide operating ranges increases power consumption and circuit area.
Innovation Solution
A hybrid data storage circuit that operates as a pulse latch for high-frequency modes and switches to a master-slave flip-flop for reduced power modes, sharing circuitry to reduce additional circuitry and power consumption, with a control circuit selecting between these modes based on performance efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data storage circuits are designed for high-frequency operation with narrow setup and hold times, then productivity is improved, but use of energy increases
Solution Approach 1:
The data storage circuit dynamically switches between two operational modes: a first mode for high-frequency operation with narrow setup and hold times, and a second mode for low-power operation. This dynamic adaptation allows the circuit to optimize between productivity and energy consumption based on operational requirements, resolving the contradiction by making the system's characteristics changeable rather than fixed
Solution Approach 2:
The invention changes key timing parameters (setup time and hold time) by switching between two distinct operational modes. In the first mode, the circuit operates with narrow setup and hold times for high-speed performance, while in the second mode, it operates with wider timing requirements for reduced power consumption. This parameter change allows the circuit to adapt its characteristics to different operational demands, resolving the contradiction between productivity and energy use
2Adaptability or versatility
If data storage circuits are designed to operate over a broad range of power supply voltage levels, then adaptability is improved, but device complexity increases
Solution Approach 1:
The data storage circuit is segmented into two distinct operational modes with different circuit configurations. The first mode is optimized for high-frequency operation at higher voltage levels, while the second mode is optimized for low-power operation at lower voltage levels. By dividing the operational range into segments and providing specialized circuitry for each, the invention achieves broad voltage range adaptability without requiring a single complex circuit design to handle all conditions
Solution Approach 2:
The data storage circuit is designed to perform multiple functions by operating in two modes. The same physical circuit can operate in a first mode for high-performance applications and a second mode for power-saving applications, making it universally applicable across different power supply voltage levels and performance requirements. This multi-functionality reduces the need for separate circuits for different operating conditions, thereby managing complexity while improving adaptability
Data Source
AI summary
An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.