Hybrid Layer Address Mapping for GPU Virtualization
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Solution Overview
Problem
Current GPU virtualization architectures face challenges in efficiently translating guest physical addresses to host physical addresses, particularly in systems with multiple virtual machines sharing a physical GPU, leading to performance degradation and security concerns due to complex shadow page table management and overhead costs.
Innovation Solution
A hybrid layer of address mapping (HLAM) is introduced, utilizing an I/O Memory Management Unit (IOMMU) to directly remap guest page numbers to host page numbers without relying on shadow page tables, while retaining a global shadow Graphics Translation Table for address ballooning, thereby simplifying the translation process and reducing overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If shadow page tables are used for address translation in GPU virtualization, then multiple virtual machines can share a physical GPU, but the complexity of shadow page table management increases and performance degrades due to synchronization and write-protection overhead
Solution Approach 1:
The patent extracts the shadow page table synchronization and write-protection functions from the address translation process. By using IOMMU for direct address translation and only maintaining shadow page tables for address ballooning operations, the system removes the performance-critical path from shadow page table management while preserving multi-VM support capabilities.
Solution Approach 2:
The patent segments the address translation functionality into two parts: (1) IOMMU handles the critical path of guest physical address to host physical address translation, and (2) shadow page tables are only used for address ballooning operations. This segmentation eliminates the overhead of synchronizing shadow page tables for every memory access while maintaining the ability to support multiple VMs.
2Adaptability or versatility
If shadow page tables with write-protection are used for address translation, then memory sharing among VMs is enabled, but performance degrades due to synchronization overhead and write-protection checks
Solution Approach 1:
The patent removes shadow page table synchronization and write-protection checks from the critical address translation path by delegating these functions to the IOMMU. The IOMMU hardware directly translates guest physical addresses to host physical addresses without requiring software intervention for each memory access, thereby eliminating the performance overhead while preserving memory sharing capabilities through address ballooning when needed.
3Productivity
If hardware address translation is used for GPU virtualization, then near-native performance is achieved, but the GPU can only be passed through to one VM at a time
Solution Approach 1:
The patent introduces IOMMU as an intermediary between the GPU and multiple VMs. The IOMMU translates guest physical addresses from different VMs to host physical addresses, enabling multiple VMs to access the same physical GPU simultaneously. This intermediary layer provides the address translation functionality needed for GPU sharing while maintaining the performance characteristics of hardware-based translation without the overhead of shadow page table management.
Data Source
AI summary
An apparatus and method are described for implementing a hybrid layer of address mapping for an IOMMU implementation. For example, one embodiment of a graphics processing apparatus comprises: virtualization circuitry to implement a virtualized execution environment in which a plurality of guest virtual machines (VMs) are to execute and share execution resources of the graphics processing apparatus; an input/output (I/O) memory management unit (IOMMU) to couple the VMs to one or more I/O devices; a hybrid layer address mapping (HLAM) module to combine entries from a per-process graphics translation table (PPGTT) with entries from a global graphics translation table (GGTT) into a first integrated page table, the first integrated page table mapping PPGTT guest page numbers (GPNs) to host page numbers (HPNs) and mapping GGTT virtual GPNs to HPNs; the HLAM to transform a GGTT GPN into a virtual GPN usable to access a corresponding HPN within the first integrated page table in response to a GGTT read/write operation generated by a first guest virtual machine (VM).