Hybrid Layout Structural Testing Without Scan Chain
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Solution Overview
Problem
Existing electronic device testing methods require a scan chain, which increases overhead and limits test coverage, especially in structural tests, as they necessitate separate components and have incomplete test coverage due to a small number of cases being tested.
Innovation Solution
An electronic device and method that allow structural testing without a scan chain by generating a hybrid layout using a design for test (DFT) layout and electronic design automation (EDA) tools, incorporating bypass storage elements and repair logic to perform tests internally, eliminating the need for scan chain components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a scan chain is used for structural testing, then test coverage is improved, but device complexity and overhead increase
Solution Approach 1:
The patent extracts the testing functionality from the traditional scan chain structure and integrates it directly into the functional circuit elements themselves. The flip-flops and logic elements are modified to include test modes that enable structural testing without requiring separate scan chain components, thereby achieving high test coverage while reducing device complexity and overhead.
Solution Approach 2:
The patent makes the functional circuit elements multi-functional by enabling them to operate in both normal functional modes and test modes. The same flip-flops and logic elements used for functional operation are also used for structural testing, eliminating the need for dedicated scan chain components and achieving both functional performance and test coverage.
2Reliability
If a scan chain is used for structural testing, then test coverage is improved, but manufacturing cost increases
Solution Approach 1:
The patent removes the need for separate scan chain components and their associated manufacturing processes. By integrating testing functionality into the existing functional circuit elements, the patent reduces the number of components that need to be manufactured and assembled, thereby reducing manufacturing cost while maintaining high test coverage.
Solution Approach 2:
The patent achieves cost reduction by making existing functional elements serve dual purposes - both functional operation and structural testing. This eliminates the need to manufacture and integrate separate scan chain components, reducing overall manufacturing complexity and cost while achieving comprehensive test coverage.
3Reliability
If functional test cases are increased, then test coverage is improved, but test time increases
Solution Approach 1:
The patent performs preliminary setup by configuring the circuit elements into test modes before actual testing begins. Test patterns are pre-generated and loaded into the integrated test structures, allowing rapid execution of comprehensive structural tests without the time penalty of setting up separate scan chain infrastructure or executing numerous functional test cases.
Solution Approach 2:
The patent replaces the mechanical approach of physically executing many functional test cases with an automated structural testing approach. Test patterns are automatically generated and applied to the integrated test structures, which directly observe internal signal values, thereby achieving comprehensive test coverage in significantly reduced time compared to exhaustive functional testing.
Data Source
AI summary
Disclosed is a method of testing an electronic device, which includes receiving, by a computer, a circuit layout, generating, by the computer, a design for test (DFT) layout from the circuit layout, generating, by the computer, a test pattern by using an electronic design automation (EDA) tool, based on the DFT layout, and generating, by the computer, a hybrid layout from the DFT layout, and the electronic device manufactured by using the hybrid layout is tested by using the test pattern.