Hybrid LDPC Decoding with Decoder Switching for NAND Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory systems using flash memory, such as SSDs, face limitations in error correction capabilities and power consumption due to the trade-offs between bit-flipping (BF) and min-sum (MS) decoders, where BF decoders offer higher throughput but lower correction capability, and MS decoders provide higher correction but consume more power.
Innovation Solution
Implementing a hybrid decoding scheme that utilizes a q-bit bit-flipping (q-BF) decoder and a min-sum (MS) decoder in a memory controller, where the decoders exchange information to determine the most suitable decoder for initial decoding based on the unsatisfied check count, allowing iterative decoding between the two to maximize correction capability and minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a bit-flipping (BF) decoder is used for decoding LDPC codewords, then throughput is higher and power consumption is lower, but correction capability is limited and performance has an error floor
Solution Approach 1:
The system dynamically selects between BF decoder and MS decoder based on the error rate of the input codeword. When error rate is below a threshold, the high-speed BF decoder is used; when error rate exceeds the threshold, the high-correction-capability MS decoder is activated. This dynamic adaptation resolves the contradiction by matching decoder performance to actual error conditions.
Solution Approach 2:
The system changes the operational parameters by switching between two different decoding algorithms (BF and MS) based on the error rate parameter. The threshold-based selection mechanism allows the system to adaptively adjust which decoder is active, thereby optimizing the balance between throughput and correction capability according to the actual data conditions.
2Reliability
If a min-sum (MS) decoder is used for decoding LDPC codewords, then correction capability is much higher, but throughput is lower and power consumption is higher
Solution Approach 1:
The system dynamically selects between BF decoder and MS decoder based on the error rate of the input codeword. When error rate is below a threshold, the high-speed BF decoder is used; when error rate exceeds the threshold, the high-correction-capability MS decoder is activated. This dynamic adaptation resolves the contradiction by matching decoder performance to actual error conditions.
Solution Approach 2:
The system changes the operational parameters by switching between two different decoding algorithms (BF and MS) based on the error rate parameter. The threshold-based selection mechanism allows the system to adaptively adjust which decoder is active, thereby optimizing the balance between throughput and correction capability according to the actual data conditions.
3Device complexity
If a single decoder type is used in the memory controller, then device complexity is lower, but the system cannot adapt to varying error rates throughout the life of the NAND flash storage
Solution Approach 1:
The decoder function is segmented into two separate decoder units: a BF decoder optimized for low error rates and an MS decoder optimized for high error rates. Each decoder handles specific error rate ranges, allowing the system to adapt to varying conditions throughout the NAND flash lifecycle without requiring a single complex adaptive algorithm.
Solution Approach 2:
The system dynamically selects between BF decoder and MS decoder based on the error rate of the input codeword. When error rate is below a threshold, the high-speed BF decoder is used; when error rate exceeds the threshold, the high-correction-capability MS decoder is activated. This dynamic adaptation resolves the contradiction by matching decoder performance to actual error conditions.
Data Source
AI summary
Memory controllers, decoders and methods execute a hybrid decoding scheme with exchange of information between multiple decoders. A first type of decoder performs initial decoding of a codeword when an unsatisfied check (USC) count of the codeword is less than a threshold, and a second type of decoder performs decoding of a codeword when the USC count of the codeword is greater than or equal to the threshold. During decoding by one of the decoders, the controller generates information from an output of that decoder and send the information to the other decoder, which the other decoders uses in decoding. The codeword is routed and rerouted between the decoders, which may include a q-bit bit-flipping (q-BF) decoder and a min-sum (MS) decoder, based on conditions that occur during decoding.