Hybrid Non-Binary LDPC Decoder With Galois Field Transformation

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Solution Overview

Problem

Existing data processing systems face challenges in effectively decoding data due to errors introduced during transmission and storage, particularly in systems using low density parity check (LDPC) decoders, where the difference in Galois fields between variable nodes and check nodes complicates error correction.

Innovation Solution

A hybrid min-sum based non-binary low density parity check decoder is introduced, utilizing variable and check node processors with different Galois fields, where messages are renormalized and transformed to ensure accurate decoding by mapping between fields, enabling efficient error detection and correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional LDPC decoders use uniform Galois fields for both variable nodes and check nodes, then the decoding process is simpler, but error correction effectiveness deteriorates when handling different node types

Engineering Contradiction:
Improveerror correction effectivenessVSAvoiddecoder structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The decoder is segmented into two distinct processors: a variable node processor operating in GF(2^m) and a check node processor operating in GF(2^n), where m ≠ n. This segmentation allows each processor to be optimized for its specific node type, improving error correction effectiveness while managing complexity through functional separation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different Galois fields are assigned to different parts of the decoder based on their functional requirements. The variable node processor uses GF(2^m) while the check node processor uses GF(2^n), allowing each local component to have the optimal field characteristics for its specific error correction tasks.

Inventive Principle:
Principle #3Local quality

2Reliability

If hybrid Galois fields are used in variable and check node processors, then error detection and correction capabilities are improved, but message transformation and renormalization complexity increases

Engineering Contradiction:
Improveerror detection capabilityVSAvoidmessage transformation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Message transformation circuits and renormalization circuits act as intermediaries between the variable node processor and check node processor. These intermediary components handle the complex field conversions and renormalization operations, isolating the complexity from the core processing logic while enabling effective error detection through hybrid Galois fields.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If messages are renormalized and transformed between different Galois fields, then decoding accuracy is improved, but processing time and computational overhead increase

Engineering Contradiction:
Improvedecoding accuracyVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

Renormalization operations are performed preliminarily on messages before they are passed between processors of different Galois fields. By pre-processing messages to ensure proper normalization, the system avoids iterative corrections later, improving decoding accuracy while minimizing additional processing time through upfront preparation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9048874B2Min-sum based hybrid non-binary low density parity check decoder
Publication Date: 2015.06.02 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US9048874B2 patent drawing
  • US9048874B2 patent drawing
  • US9048874B2 patent drawing

AI summary

An apparatus for decoding data includes a variable node processor, a check node processor, and a field transformation circuit. The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The variable node processor and the check node processor comprise different Galois fields. The field transformation circuit is operable to transform the variable node to check node messages from a first of the different Galois fields to a second of the Galois fields.