Hybrid LDPC Decoding for NAND Flash Error Correction
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Solution Overview
Problem
Current memory systems using NAND-type flash memory face limitations in error correction, particularly as the device ages, with bit-flipping (BF) decoders providing higher throughput but limited correction capability and min-sum (MS) decoders offering higher correction capability but lower throughput and higher power consumption.
Innovation Solution
Implementing a hybrid decoding scheme that switches between BF and MS decoders based on the unsatisfied check (USC) count, using BF for initial decoding when errors are low and switching to MS when errors exceed the BF's correction capability, and vice versa, to optimize throughput and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a bit-flipping (BF) decoder is used for decoding LDPC codewords, then throughput is higher and power consumption is lower, but correction capability is limited and performance has an error floor
Solution Approach 1:
The system dynamically switches between BF decoder and MS decoder based on the error condition of the codeword. The BF decoder is used for initial decoding when errors are within correction capability, and the MS decoder is activated when the codeword exceeds BF's correction capability or when an error floor is detected, optimizing both throughput and correction capability adaptively
Solution Approach 2:
The system changes the decoding parameter (decoder type) based on the error condition. By monitoring whether the codeword exceeds correction capability or detecting error floor conditions, the system switches between different decoder algorithms (BF and MS) to maintain optimal performance across varying error rates
2Reliability
If a min-sum (MS) decoder is used for decoding LDPC codewords, then correction capability is much higher, but throughput is lower and power consumption is higher
Solution Approach 1:
The system dynamically selects the decoder type based on real-time error conditions. The MS decoder is reserved for cases where high correction capability is needed (when codeword exceeds BF capability or error floor detected), while BF decoder handles normal cases, thus maintaining high throughput while providing high correction capability when necessary
Solution Approach 2:
The system changes the decoding algorithm parameter based on error severity. By switching from BF to MS decoder when correction capability is insufficient, the system optimizes the balance between correction capability and throughput by using the more powerful MS decoder only when needed
3Device complexity
If a single decoder type is used throughout the device lifecycle, then device complexity is reduced, but performance degrades as the device ages and error rates increase
Solution Approach 1:
The system dynamically adapts its decoding strategy based on the device lifecycle and error conditions. By monitoring error rates and switching between BF and MS decoders, the system maintains high correction performance throughout the device lifecycle without requiring complex hardware reconfiguration
Solution Approach 2:
The system implements a universal decoding architecture that can perform both BF and MS decoding. This multi-functional decoder assembly handles different error conditions and device lifecycle stages, providing adaptability without requiring separate dedicated hardware for each decoder type
Data Source
AI summary
Memory controllers, decoders and methods execute a hybrid decoding scheme. An initial iteration of decoding of a codeword is performed using a bit-flipping (BF) decoder or a min-sum (MS) decoder depending on whether or not an unsatisfied check (USC) count of the codeword is less than a threshold. For this initial iteration, the BF decoder is used when the USC count is less than the threshold, and MS decoder when the USC count is greater than or equal to the threshold. When decoding of the codeword is initially performed with the BF decoder, decoding continues with the BF decoder until a first set of conditions is satisfied or the codeword is successfully decoded. When decoding of the codeword is performed with the MS decoder, decoding continues with the MS decoder until a second set of conditions is satisfied.