Hybrid LDPC Decoding for Low-Power Memory Error Correction

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Solution Overview

Problem

Conventional bit-flipping (BF) decoders perform poorly on irregular low-density parity-check (LDPC) codes due to low column weights, while min-sum (MS) decoders consume more power, making them unsuitable for mobile and client SSD applications.

Innovation Solution

A memory controller that employs a hybrid decoding approach, using BF decoding for variable nodes with column weights greater than or equal to a threshold and MS decoding for those with lower column weights, allowing for efficient error correction with reduced power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If bit-flipping (BF) decoding is used for irregular LDPC codes, then power consumption is reduced, but error correction performance deteriorates due to low column weights

Engineering Contradiction:

Improvepower consumptionVSAvoiderror correction performance

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies different decoding algorithms to different variable nodes based on their column weights. Specifically, BF decoding is applied to variable nodes with column weight greater than or equal to a threshold, while MS decoding is applied to variable nodes with column weight less than the threshold. This local differentiation resolves the contradiction by optimizing the decoding approach for each node's characteristics, maintaining low power consumption for most nodes while improving error correction performance for critical low-weight nodes.

Inventive Principle:

Principle #3Local quality

2Reliability

If min-sum (MS) decoding is used to improve error correction performance, then reliability is improved, but power consumption increases

Engineering Contradiction:

Improveerror correction performanceVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements partial MS decoding by applying it only to a subset of variable nodes (those with column weight less than the threshold) rather than all variable nodes. This partial application of the more powerful but power-intensive MS algorithm achieves sufficient error correction performance while avoiding the full power consumption cost of universal MS decoding.

Inventive Principle:

Principle #16Partial or excessive action

3Device complexity

If conventional BF decoding is used on irregular LDPC codes, then device complexity is low, but decoding performance deteriorates

Engineering Contradiction:

Improvedecoder complexityVSAvoiddecoding performance

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent differentiates the decoding approach based on local characteristics of variable nodes (column weights). By identifying and separately handling variable nodes with low column weights through MS decoding, the system improves overall decoding performance without significantly increasing device complexity, as the majority of nodes still use the simpler BF approach.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS11356123B2Memory system with low-complexity decoding and method of operating such memory system

Publication Date: 2022.06.07 SK HYNIX INC

AI summary

Memory controllers, decoders and methods to selectively perform bit-flipping (BF) decoding and min-sum (MS) decoding on codewords of an irregular low-density parity-check (LDPC) code. Bit-flipping (BF) decoding is executed with respect to variable nodes having relatively high column weights. MS decoding is executed with respect to variable nodes having relatively low column weights. A column-weight threshold is used to group the variable nodes into the higher and lower column weight groups. The two decoding techniques exchange results during the overall decoding process.