Hybrid Lead Frame Multi-Chip Semiconductor Device
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Solution Overview
Problem
Traditional power devices with stacked multi-chip packages, such as DC-DC converters, suffer from poor heat dissipation due to their thick chip and clip stacking structure, which hampers their thermal performance.
Innovation Solution
A lead frame unit with a bridge-type metal clip and support pads is used to connect high-side and low-side MOSFETs, allowing for improved heat dissipation through a thinner package structure and optimized electrical connections, while a plastic package layer reduces the Ron (resistance) of the MOSFETs and facilitates the use of bridge clips for enhanced thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional wire bonding or metal clip is used for interconnection in a power device, then electrical connection is achieved, but the package structure becomes thick and heat dissipation performance deteriorates
Solution Approach 1:
The patent transitions from traditional vertical stacking (Z-dimension) to a planar arrangement (X-Y plane) by using a lead frame with multiple paddles arranged in a plane. Chips are mounted on different paddles rather than stacked vertically, reducing the thickness dimension while maintaining electrical connections through the lead frame structure.
Solution Approach 2:
The lead frame is divided into multiple separate paddles (first paddle, second paddle, third paddle, fourth paddle) that are electrically isolated from each other. This segmentation allows chips to be mounted on different paddles in a planar configuration, enabling independent thermal paths for each chip while maintaining electrical functionality.
2Adaptability or versatility
If chip and clip stacking structure is used, then multi-chip functionality is achieved, but the package thickness increases and thermal management becomes difficult
Solution Approach 1:
The patent arranges multiple chips in a planar configuration on different paddles of the lead frame rather than stacking them vertically. This dimensional change from Z-stack to XY-plane arrangement reduces package thickness while achieving multi-chip functionality through the lead frame's electrical interconnection structure.
Solution Approach 2:
The lead frame serves multiple functions simultaneously: it provides mechanical support for mounting multiple chips, establishes electrical connections between chips and external terminals, and facilitates heat dissipation through its thermal pathways. This multi-functionality eliminates the need for separate interconnection structures.
3Adaptability or versatility
If traditional stacked multi-chip package is used, then DC-DC converter functionality is achieved, but thermal performance deteriorates due to thick structure
Solution Approach 1:
The lead frame is segmented into multiple electrically isolated paddles, each capable of mounting a chip. This segmentation creates independent thermal zones for each chip, allowing heat to be dissipated through separate pathways rather than being trapped in a thick stacked structure, thereby improving overall thermal performance.
Solution Approach 2:
By arranging chips in a planar configuration on different paddles rather than stacking them vertically, the patent reduces the thermal resistance path length. Heat can be more efficiently conducted from each chip through its respective paddle to the heat sink or PCB, improving thermal performance while maintaining DC-DC converter functionality.
Data Source
AI summary
A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.