Hybrid Lock Detector Using Pulse-Width Gating for Fast PLL Lock
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Solution Overview
Problem
Conventional counter-based lock detectors require thousands of clock cycles to achieve locking accuracy, wasting additional cycles due to frequency differences between VCO and reference frequencies, and are inefficient in applications with limited clock cycles, such as memory interfaces.
Innovation Solution
A hybrid lock detector combining an analog phase comparator and digital lock detector, generating an enable signal based on pulse width comparisons and using a digital circuit to determine lock status within a reduced decision window, allowing for fast and accurate lock detection without sacrificing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional counter-based lock detectors are used to achieve locking accuracy, then the locking accuracy specification is met, but thousands of clock cycles are required which wastes time
Solution Approach 1:
The lock detection process is segmented into two distinct phases: an initial analog phase detection stage that quickly determines whether locking has occurred, and a subsequent digital counter-based stage that verifies the locking accuracy specification. This segmentation allows the system to avoid counting thousands of clock cycles while still meeting the accuracy requirement, as the analog stage provides rapid initial detection and the digital stage only performs limited verification counting.
2Speed
If lock detection is performed during initial phase locking when VCO frequency differs significantly from reference frequency, then detection can occur early, but false unlock signals are generated
Solution Approach 1:
Different detection methods are applied at different stages of the locking process. During initial phase locking when VCO frequency differs significantly from reference frequency, an analog phase comparator is used that is insensitive to frequency differences. Once the PLL approaches lock, a digital counter-based method takes over to verify the locking accuracy specification. This local quality approach ensures reliable detection at each stage without generating false unlock signals.
3Measurement precision
If thousands of clock cycles are counted for lock detection, then locking accuracy is achieved, but the process is too slow for applications with limited clock cycles
Solution Approach 1:
The analog phase comparator performs preliminary detection of lock status before the digital counter begins its counting process. This preliminary action provides an early indication of whether locking has occurred, allowing the system to limit the number of clock cycles counted for verification purposes. The preliminary analog detection ensures that the subsequent digital counting process does not need to count thousands of cycles, thereby improving productivity while maintaining accuracy.
Data Source
AI summary
The invention concerns an apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to generate an enable signal in response to (i) a comparison of a width of an up pulse and a pre-determined width and (ii) a comparison of a width of a down pulse and the pre-determined width. The up pulse and the down pulse may be generated in response to a comparison of a feedback signal and a reference signal. The enable signal may be active when both the comparisons are within a pre-determined threshold. The digital circuit may be configured to generate an output signal representing a lock status between (i) the feedback signal and (ii) the reference signal. The lock status may be determined (a) during a decision window based on a number of pulses of the reference signal and (b) when the enable signal is active.