Hybrid Lock Assignment for Shared Memory Concurrency

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Solution Overview

Problem

In software transactional memory (STM) implementations, false conflicts arise due to the assignment of locks without considering application characteristics, leading to high runtime overheads and performance issues, as distinct memory locations are mapped to the same lock, causing unnecessary aborts and rollbacks.

Innovation Solution

A hybrid lock assignment technique is employed, combining static compiler-driven lock assignment for must-alias shared memory locations and runtime hash-function-based assignment for others, using a Compiler Lock Assignment Table (CLAT) and Runtime Lock Table (RLT) to selectively reduce false conflicts and improve concurrency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If runtime hash-function-based lock assignment is used, then ease of operation is improved, but false conflicts increase leading to higher transaction aborts

Engineering Contradiction:

Improveease of operationVSAvoidtransaction aborts

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The patent segments the lock assignment process into two distinct phases: compile-time static assignment for must-alias locations and runtime dynamic assignment for other locations. This segmentation allows each phase to optimize for its specific characteristics, reducing false conflicts while maintaining ease of operation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies different lock assignment strategies to different memory locations based on their aliasing characteristics. Must-alias locations receive static lock assignment to eliminate false conflicts, while non-must-alias locations use runtime assignment for flexibility. This local differentiation optimizes both reliability and ease of operation for each location type.

Inventive Principle:

Principle #3Local quality

2Reliability

If compile-time lock assignment is used, then false conflicts are reduced, but device complexity increases due to analysis requirements

Engineering Contradiction:

Improvefalse conflictsVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies compile-time lock assignment only to a subset of memory locations (must-alias locations) rather than all locations. This partial application reduces the analysis complexity required while still eliminating false conflicts where they occur, avoiding the excessive complexity that would result from analyzing every memory location.

Inventive Principle:

Principle #16Partial or excessive action

3Device complexity

If all memory locations use the same lock, then device complexity is reduced, but false conflicts increase causing performance degradation

Engineering Contradiction:

Improvedevice complexityVSAvoidruntime performance

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent differentiates lock assignment strategies based on the local characteristics of memory locations. Must-alias locations receive specialized static lock assignment to prevent false conflicts and improve performance, while other locations use simpler runtime assignment. This local differentiation maintains overall simplicity while boosting productivity where needed.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS9189297B2Managing shared memory

Publication Date: 2015.11.17 HEWLETT PACKARD ENTERPRISE DEV LP

AI summary

Systems, methods, and computer-readable and executable instructions are provided for managing shared memory. A method for managing shared memory can include statically assigning a first number of locks to the shared memory during compile-time and dynamically assigning a second number of locks to the shared memory during runtime.