Hybrid Loop Unrolled DFE Architecture for Power-Efficient Signal Correction
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Solution Overview
Problem
Conventional distortion correction techniques in semiconductor memory devices are inadequate, leading to increased data errors due to inter-symbol interference, and loop unrolling methods, while effective, consume more power.
Innovation Solution
A hybrid loop unrolled decision feedback equalizer (DFE) architecture that uses loop unrolling for power-efficient distortion correction but reverts to a traditional receiver architecture when DFE is not used to conserve power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If loop unrolling is used to correct distortions quickly, then data error reduction is improved, but power consumption increases
Solution Approach 1:
The patent implements a dynamic architecture that can switch between traditional sequential DFE processing and loop unrolled parallel processing modes. The system adapts its processing structure based on operational requirements, enabling fast parallel distortion correction when needed while reverting to power-efficient sequential processing during normal operation, thus resolving the contradiction between speed and power consumption
Solution Approach 2:
The patent changes the processing parameter from sequential to parallel by unrolling the feedback loop into multiple parallel processing paths. This parameter change enables simultaneous correction of multiple data bits, significantly reducing processing time and data errors while allowing the system to toggle between modes to control power consumption
2Speed
If loop unrolling is implemented to process decisions in parallel, then distortion correction speed is improved, but device complexity increases
Solution Approach 1:
The patent segments the feedback loop into multiple parallel processing paths, where each path handles a specific data bit correction. This segmentation enables simultaneous processing of multiple bits, improving distortion correction speed while organizing the complexity into manageable modular units that can be selectively activated
3Reliability
If DFE technique is always used to correct inter-symbol interference, then data reliability is improved, but power consumption increases
Solution Approach 1:
The patent creates a dynamic system that can adaptively switch between traditional DFE and loop unrolled DFE modes based on operational conditions. The architecture includes control logic that determines when fast parallel processing is necessary to correct data errors versus when standard sequential processing suffices, thereby maintaining data reliability while minimizing power consumption
Data Source
AI summary
A keeper device is used in a hybrid loop unrolled DFE circuit to selectively output signals from equalizers corresponding to a specific possibility of the values of the previous bit (e.g., logical high or logical low) when DFE technique is not used. Those equalizers corresponding to possibilities other than the specific possibility of the values of the previous bit are disabled in the hybrid loop unrolled DFE circuit. As such, the hybrid loop unrolled DFE circuit saves power when the DFE technique is not used since only a portion of the total equalizers in the hybrid loop unrolled DFE circuit are powered.