Hybrid Many-Core Device With Programmable Logic Fabric
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Solution Overview
Problem
Designing many-core devices that can efficiently accommodate varying accelerator requirements and manage intermittent memory access across multiple agents is challenging, often resulting in wasted resources and complex memory coordination.
Innovation Solution
A hybrid programmable logic device integrating programmable field programmable gate array logic fabric and many-core distributed processing subsystem, allowing for late binding of hardware acceleration functions and dynamic routing through a shared interconnect, with tiled processors and a hardened data bus for efficient data transfer and power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If processors are integrated into the programmable logic fabric with dimensions that are multiples of the logic element dimensions, then devices with varying ratios of processors to logic elements can be efficiently assembled, but the device complexity increases due to the need for tiled processor arrangements and shared interconnects
Solution Approach 1:
The patent segments the processor integration into standardized tiles where each processor occupies a defined area within the programmable logic fabric. This segmentation allows processors to be arranged in various configurations (different ratios of processors to logic elements) by simply changing the number and arrangement of tiles, thereby achieving device reconfigurability without proportionally increasing integration complexity.
Solution Approach 2:
The patent creates a universal integration framework where the same programmable logic fabric and interconnect infrastructure can accommodate different numbers and arrangements of processors. The shared interconnect and common dimension-based tiling approach serve multiple configuration requirements simultaneously, making the device adaptable to varying application needs without requiring separate integration schemes for each configuration.
2Device complexity
If a shared interconnect is used for routing between processors and logic elements, then device complexity is reduced compared to dedicated interconnects, but the speed of data transfer between processors and memory may be limited by intermittent access patterns
Solution Approach 1:
The patent implements a dynamic routing mechanism within the shared interconnect that adapts to the access patterns of multiple agents. The interconnect can dynamically allocate bandwidth and routing paths based on which processors are actively accessing memory and what their access patterns are, thereby maintaining high data transfer speeds despite the shared nature of the interconnect and intermittent access requirements.
Data Source
AI summary
The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.