Hybrid MDLL/PLL Clock Circuit for Uniform Phases and Lower Jitter
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Solution Overview
Problem
Existing multiplying delay-line loop (MDLL) designs suffer from non-uniform output phases and accumulated jitter due to differential propagation delays in the front-end selection multiplexer and subsequent delay elements, leading to errors in phase interpolators and M-cycle accumulated jitter.
Innovation Solution
A hybrid circuit combining MDLL and PLL, utilizing a chain of inverting delay multiplexers in a ring configuration with a propagation delay control circuit, allowing both rising and falling edges of the forwarded clock to correct the phase of the local clock, reducing accumulated jitter by half through interpolation based on transistor channel widths and control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If only the rising edge is fed into delay line in MDLL, then the structure is simple, but M-cycle accumulated jitter occurs
Solution Approach 1:
The patent segments the single-edge feedback into dual-edge feedback paths. The rising edge and falling edge are separately processed through delay elements, with the falling edge path including an additional inverter. This segmentation allows both edges to contribute to phase correction, reducing accumulated jitter while maintaining structural clarity.
Solution Approach 2:
The patent applies inversion by using the falling edge (inverted state) in addition to the rising edge for feedback. By inverting the clock signal to access both edges, the system transforms a single-edge limitation into a dual-edge advantage, reducing jitter accumulation without significantly increasing complexity.
2Ease of manufacture
If front-end selection multiplexer has different propagation delay than delay elements, then the circuit is easier to implement, but non-uniform output phases are produced
Solution Approach 1:
The patent applies local quality by making the delay elements in the delay chain have uniform, matched delay characteristics, while allowing the front-end multiplexer to have different delay. This localized optimization ensures that the critical delay-matched paths (through the delay chain) produce uniform phases, while the multiplexer can be implemented more simply without affecting overall phase uniformity.
Solution Approach 2:
The patent changes the delay parameter of the delay elements to be uniform and matched across all elements in the chain. By carefully controlling and matching the delay parameter of each delay element, the system compensates for the multiplexer's different delay, ensuring uniform output phases at the phase interpolator inputs.
3Reliability
If PLL is used to form high-frequency local clock, then jitter filtering is better, but jitter tracking is worse
Solution Approach 1:
The patent merges the MDLL and PLL architectures into a hybrid system. The delay chain with uniform delay elements provides the jitter tracking capability of MDLL, while the phase detector and feedback mechanism provide the jitter filtering capability of PLL. This combination allows the system to simultaneously achieve both jitter filtering and jitter tracking performance.
Solution Approach 2:
The patent creates a composite clock generation system that combines elements of both MDLL and PLL architectures. By integrating the delay-chain-based phase multiplication of MDLL with the phase-detection-based feedback control of PLL, the system achieves composite performance that leverages the strengths of both approaches for jitter filtering and tracking.
Data Source
AI summary
A circuit for generating a clock signal formed as a hybrid of a multiplying delay-locked loop (MDLL) and a phase locked loop (PLL). In one embodiment a chain of inverting delay multiplexers is connected in a ring configuration capable of operating as a ring oscillator, with a first delay multiplexer in the ring configured to substitute a feed-in clock signal for the feedback clock generated by the ring oscillator when an edge, either rising or falling, is received at the forwarded clock input. The first delay multiplexer may also be configured to interpolate between the phase of the feedback clock and the phase of the feed-in clock. The interpolation may be based on transistor channel widths and the value of a control signal, and results in behavior intermediate to that of an MDLL and that of a PLL.