Hybrid Memory Interface With 24 Conductors for LPDDR5 Bandwidth
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Solution Overview
Problem
Conventional memory systems face challenges in balancing power consumption, latency, bandwidth, and cost, particularly in mobile communication devices, where doubling the number of conductors or clock frequency to increase bandwidth leads to space and routing issues.
Innovation Solution
A hybrid memory system with 24 data conductors, tailored pin layout, and encoding techniques to enhance bandwidth without doubling pin counts or clock speed, incorporating error correction codes and optimized routing and encoding logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of data conductors is increased from 16 to 24, then bandwidth is improved, but device complexity and routing difficulty increase
Solution Approach 1:
The patent segments the data conductors into two distinct groups: 16 conventional LPDDR5 conductors and 8 additional conductors. This segmentation allows the system to maintain backward compatibility while adding enhanced bandwidth capability through a separate conductor set, thereby managing complexity through modular organization.
Solution Approach 2:
The patent introduces a new dimension to the data transmission architecture by adding 8 additional conductors beyond the standard 16, creating a 24-conductor interface. This dimensional expansion enables higher bandwidth without requiring a complete redesign of the entire conductor architecture, thus balancing performance improvement with manageable complexity.
2Productivity
If the clock frequency is doubled to increase bandwidth, then productivity improves, but electromagnetic interference and signal integrity issues worsen
Solution Approach 1:
The patent changes the physical parameter of conductor count rather than increasing clock frequency to achieve bandwidth improvement. By adding 8 data conductors to create a 24-conductor interface, the system increases bandwidth capacity without the electromagnetic interference and signal integrity problems associated with doubling clock speed.
3Productivity
If the pin count is doubled to accommodate more conductors, then bandwidth improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent segments the pin allocation by maintaining the original 16-pin LPDDR5 interface structure and adding 8 additional pins for the enhanced conductors. This segmented approach allows the memory controller to handle both conventional and enhanced modes, simplifying manufacturing compared to a complete pin count doubling while still achieving higher bandwidth.
Data Source
AI summary
A hybrid memory system with improved bandwidth is disclosed. In one aspect, a memory system is provided that increases bandwidth relative to the JEDEC low-power double data rate version 5 (LPDDR5) standard. This improvement is made possible by increasing a data conductor count from sixteen to twenty-four. Optionally, the bandwidth may be further improved by increasing a clock frequency from a first value to a second value. This allows the hybrid memory system to provide improved bandwidth without the complications of merely doubling pin counts or doubling clock speed. Further, coding techniques tailored to the pin count and pin layout are provided.