Hybrid Memory Address Interleaving for Transparent NUMA Allocation
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Solution Overview
Problem
Existing computer systems with mixed-mode memory architectures face complexity in memory allocation due to differentiated memory capabilities, leading to variable application performance, as the operating system lacks sensitivity to memory latency and cannot manage these differences effectively.
Innovation Solution
Implementing a hybrid memory mode where near and far memories are interleaved in a fine-grained manner, presenting a unified non-uniform memory access (NUMA) domain to the operating system, with hardware managing memory location details transparently, and using a system address map to ensure uniform performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If mixed-mode memory architecture with differentiated NUMA ranges is used, then system memory capacity and speed are increased, but operating system complexity and memory allocation difficulty increase
Solution Approach 1:
The patent merges near memory and far memory into a unified memory space by interleaving their address ranges. The system presents a single contiguous NUMA domain to the operating system, combining previously separate memory regions into one integrated structure that eliminates the need for differentiated management while maintaining performance benefits.
Solution Approach 2:
The patent segments the unified memory space into interleaved address ranges, where alternate address ranges map to near memory and far memory respectively. This segmentation allows the system to maintain fine-grained control over memory placement while presenting a unified interface, enabling performance optimization without increasing OS complexity.
2Quantity of substance
If mixed-mode memory architecture with differentiated NUMA ranges is used, then system memory capacity is increased, but application performance uniformity deteriorates
Solution Approach 1:
The patent applies local quality by assigning different memory types to specific address ranges within the unified space. Near memory is assigned to certain interleaved address ranges while far memory is assigned to alternate ranges, allowing performance-critical data to reside in faster memory while maintaining overall capacity expansion. This localized optimization ensures uniform application performance across the entire memory space.
3Adaptability or versatility
If separate NUMA ranges are presented to operating system, then memory type differentiation is maintained, but memory management transparency is reduced
Solution Approach 1:
The patent introduces an intermediary address translation layer that sits between the operating system and physical memory. This intermediary presents a unified NUMA domain to the OS while internally mapping addresses to the appropriate memory type (near or far). The translation mechanism maintains memory type differentiation and performance characteristics while providing transparent, simplified management to the operating system.
Data Source
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AI summary
In one embodiment, a processor includes: at least one core to execute instructions; memory to store an address map having a hybrid region to identify a flat two level memory address range formed of first near memory address ranges interleaved on a sub-page basis with far memory address ranges, the first near memory ranges located in a near memory to couple to the processor via a first link and the far memory address ranges located in a far memory to couple to the processor via a second link; and an address decoder coupled to the memory, the address decoder to receive a memory request for an address from the at least one core and decode the address based at least in part on the address map. Other embodiments are described and claimed.