Hybrid Memory Autonomous Save and Restore Operations

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Solution Overview

Problem

Legacy memory systems require a host throughout save and restore operations, leading to prolonged exchange times that can exceed the time available before a catastrophic event, often resulting in failure to save volatile memory to non-volatile memory, thus failing to protect against such events.

Innovation Solution

A hybrid memory system with a non-volatile memory controller that can autonomously disconnect from the host, perform read/write operations between volatile and non-volatile memory, and execute save and restore operations independently, using a command buffer and programmable sequences to handle events like power-downs without host intervention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If legacy protocols require host involvement throughout save and restore operations, then protocol compliance and host control are maintained, but operation time becomes too long to complete before catastrophic events

Engineering Contradiction:
Improvedata protection reliabilityVSAvoidsave operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The memory system performs save and restore operations autonomously without requiring host involvement during the actual data transfer. The system detects catastrophic events, initiates save operations to non-volatile memory, and completes restore operations independently, allowing these critical functions to execute quickly without host protocol overhead while maintaining data protection reliability

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system prepares save and restore capabilities in advance by maintaining non-volatile memory as a ready backup target and pre-configuring the autonomous operation framework. This preliminary preparation enables the system to immediately execute save operations when catastrophic events are detected, eliminating the time-consuming host protocol setup phase

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the memory system autonomously disconnects from the host to perform save operations, then operation speed increases, but host control and coordination are reduced

Engineering Contradiction:
Improvesave operation speedVSAvoidhost control ease
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The system segments control into two modes: host-controlled mode for normal operations and autonomous mode for catastrophic event responses. This segmentation allows the system to maintain ease of host control during routine operations while enabling high-speed autonomous save and restore operations when needed, resolving the contradiction between speed and control

Inventive Principle:
Principle #1Segmentation

3Reliability

If multiple protocol exchanges are required to initiate and complete save operations, then protocol compliance is ensured, but the time available before catastrophic events is exceeded

Engineering Contradiction:
Improveprotocol complianceVSAvoidsave operation duration
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The system performs preliminary configuration and capability setup during host-controlled operations, so that when catastrophic events occur, the autonomous save operation can proceed with minimal protocol exchanges. The non-volatile memory target and transfer parameters are pre-established, allowing rapid execution that completes within the limited time window before catastrophic events

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9817610B1Hybrid memory systems for autonomous non-volatile memory save and restore operations
Publication Date: 2017.11.14 MARVELL ASIA PTE LTD
  • US9817610B1 patent drawing
  • US9817610B1 patent drawing
  • US9817610B1 patent drawing

AI summary

An apparatus forms a memory system that is physically populated into a host. In a powered-on state, the apparatus logically connects to the host through a host memory controller configured to receive host-initiated commands. The memory system includes a command buffer coupled to the host memory controller to receive the host-initiated commands. The memory system comprises both volatile memory (e.g., RAM) and non-volatile memory (e.g., FLASH). A non-volatile memory controller (NVC) is coupled to the volatile memory, and is also coupled to the non-volatile memory. A command sequence processor that is co-resident with the NVC responds to a trigger signal by logically disconnecting from the host, then dispatching command sequences that perform successive read/write operations between the volatile memory and the non-volatile memory. The successive read/write operations are performed even when the host is in a powered-down state.