Hybrid Memory Architecture for Bandwidth and Cost Optimization
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Solution Overview
Problem
As DDR channel scaling becomes expensive and complex beyond certain frequencies, traditional memory systems face challenges in increasing memory bandwidth without significantly increasing costs, especially when trying to enhance memory performance in electronic devices.
Innovation Solution
The implementation of a hybrid memory architecture that combines high-density memory (HDM) such as embedded DRAM, Resistive-RAM, Thyristor-RAM, or Ferroelectric-RAM with flash memory to offset the loss of memory capacity and bandwidth from removing a DDR channel, acting as a disk cache and last-level hardware managed cache to improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DDR channel frequency is increased to improve memory bandwidth, then memory performance is improved, but system cost and complexity increase drastically
Solution Approach 1:
The patent combines volatile memory (DRAM) and non-volatile memory (NAND flash) into a single hybrid memory module that interfaces through a unified channel. This merging allows the system to achieve high bandwidth through the volatile memory portion while using non-volatile memory to store less frequently accessed data, thereby improving overall memory performance without requiring multiple high-speed channels that would increase complexity
2Productivity
If DDR channel frequency is increased to improve memory bandwidth, then memory performance is improved, but system cost increases
Solution Approach 1:
The patent changes the memory architecture parameter from a single high-speed DDR channel to a hybrid memory structure with different memory types working together. This parameter change allows the system to achieve high effective bandwidth through intelligent data placement and retrieval strategies, while using cost-effective non-volatile memory for capacity and volatile memory for speed, avoiding the need for expensive high-frequency DDR channels
3Productivity
If number of DDR channels is increased to improve memory bandwidth, then memory performance is improved, but system complexity increases
Solution Approach 1:
The patent merges multiple memory types (DRAM and NAND flash) into a single hybrid memory module that operates through one channel. This consolidation provides the bandwidth benefits of multiple channels through a single unified interface, reducing the complexity of managing multiple separate memory channels while maintaining high data transfer rates
4Productivity
If number of DDR channels is increased to improve memory bandwidth, then memory performance is improved, but system cost increases
Solution Approach 1:
The patent changes the memory system parameter from multiple parallel DDR channels to a hybrid memory architecture with a single channel. This parameter change achieves comparable or superior bandwidth through the combination of fast volatile memory for frequent accesses and high-capacity non-volatile memory for bulk storage, reducing the cost associated with implementing and managing multiple high-speed channels
Data Source
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AI summary
Methods and apparatuses for providing a hybrid memory module having both volatile and non-volatile memories to replace a DDR channel in a processing system.