Hybrid Memory Bank Segmentation for Latency-Driven Energy Optimization
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Solution Overview
Problem
The increasing amounts of data stored in main memory of enterprise servers, primarily in DRAM, lead to high static energy consumption and scalability limitations due to continuous leakage and refresh power, as well as varying access latency and power consumption based on read/write operation ratios.
Innovation Solution
Implementing a hybrid main memory system that uses a mixture of Weibull distributions to model and manage memory access latency, allowing for the selective execution of operations across DRAM and NVM banks to optimize energy usage and parallelism by adjusting operation ratios and bank states based on predicted latency probabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM is used to store large amounts of application data in main memory, then data accessibility is improved, but static energy consumption increases due to continuous leakage and refresh power
Solution Approach 1:
The memory system is segmented into multiple DRAM banks, allowing selective operation of individual banks based on access patterns. The memory controller divides memory access operations across different banks, enabling some banks to be placed in lower-power states while others remain active, thus reducing overall static energy consumption while maintaining data accessibility.
Solution Approach 2:
The system dynamically changes operational parameters by adjusting the number of active DRAM banks based on the read-to-write ratio and access latency requirements. When access latency is low and read operations dominate, fewer banks need to remain active, reducing static power consumption while maintaining performance for critical data.
2Quantity of substance
If the number of DRAM banks is increased to handle large data sets, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The large memory capacity is achieved through segmentation into multiple independent DRAM banks, each managed separately by the memory controller. This modular approach allows the system to scale capacity while managing complexity through standardized bank interfaces and centralized control logic that handles bank selection and coordination.
Solution Approach 2:
Each DRAM bank is designed as a universal, multi-functional unit that can handle both read and write operations independently. The memory controller provides universal management capabilities across all banks, allowing the same hardware resources to serve multiple functions and reducing overall system complexity despite increased capacity.
3Productivity
If memory access latency is reduced to improve system performance, then productivity is improved, but energy consumption varies and may increase due to more frequent refresh operations
Solution Approach 1:
The system dynamically adjusts the number of active DRAM banks and their operational states based on real-time access patterns and latency requirements. When high performance is needed, more banks are activated with shorter refresh intervals; when performance demands are lower, banks are deactivated or placed in extended refresh cycles, optimizing the balance between productivity and energy consumption.
Solution Approach 2:
The memory controller implements feedback mechanisms that monitor access latency and read-to-write ratios, using this information to dynamically adjust bank activation states and refresh timing. This feedback loop ensures that energy consumption is optimized while maintaining the latency performance required for system productivity.
Data Source
AI summary
Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for receiving a memory access latency value including a time to perform an operation with respect to the memory bank of the plurality of memory banks, receiving a set of operation percentages including an operation percentage for each of a plurality of operations performed on the memory bank, determining a probability associated with the memory access latency value using a mixture of Weibull distributions, described herein, comparing the probability to a threshold probability to provide a comparison, and selectively executing at least one action with respect to the memory bank based on the comparison.