Hybrid Memory Unit Data Persistence via BIOS Interrupt

The patent combines DRAM and storage memory into a hybrid memory system where DRAM provides fast read/write access and storage memory provides data persistence. The two memory types are merged at the hardware level with a unified interface to the processing unit, allowing the system to enjoy both fast access speeds and data retention capabilities simultaneously.

The patent introduces a memory controller as an intermediary component that manages data transfer between DRAM and storage memory. This controller automatically copies data from DRAM to storage memory when power-off or reset events are detected, ensuring data persistence without requiring application-level intervention while maintaining fast access speeds during normal operation.

The patent applies local quality by assigning different memory types to different functional requirements: DRAM is used for actively accessed data requiring fast read/write speeds, while storage memory is used for data requiring persistence. This localized assignment allows each memory type to operate in its optimal performance regime without compromising overall system performance.

The patent segments the memory system into multiple independent memory modules (DRAM and storage memory) that can be independently managed. This segmentation allows the system to access only the necessary portion of data from fast memory while keeping other data in persistent storage, thereby maintaining fast read/write speeds for active operations while ensuring data persistence.

The patent implements self-service by enabling the memory controller to automatically detect power-off or reset conditions and autonomously trigger data copying from DRAM to storage memory without requiring software intervention. This self-managing capability reduces the complexity burden on the operating system and application software while maintaining the benefits of hybrid memory.

The patent designs the memory controller with multi-functionality to handle both normal memory access operations and emergency data preservation operations. This universal controller manages DRAM and storage memory interactions, power-off detection, and data copying functions, reducing the need for separate dedicated components and thereby mitigating the increase in device complexity.