Hybrid Volatile Non-Volatile Memory Bitcell Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current non-volatile memory technologies face challenges in scalability, endurance, and power efficiency, particularly below 65 nanometers, with flash memory not easily scalable and other technologies like ReRAM/CBRAM exhibiting unstable resistance switching and fatigue over many cycles.
Innovation Solution
Integration of volatile and non-volatile memory bitcells, allowing for the transfer of memory states between them to reduce power consumption and latency, using a bitcell circuit with volatile memory elements and non-volatile memory elements accessible via a bitline, and a method to selectively couple non-volatile memory elements between a bitline and a voltage source to transition between operation modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If flash memory devices are used for non-volatile storage, then high bit density and random access capability are achieved, but scalability below 65 nanometers becomes difficult
Solution Approach 1:
The patent merges volatile memory (DRAM) and non-volatile memory (flash) into a single hybrid bitcell structure. The volatile memory component provides fast access and the non-volatile component provides data retention, allowing the system to achieve high bit density while maintaining scalability to smaller feature sizes below 65 nanometers through standard CMOS processing.
Solution Approach 2:
The hybrid bitcell structure serves multiple functions simultaneously: it provides volatile storage for fast access, non-volatile storage for data retention, and can operate in different modes (volatile mode, non-volatile mode, or hybrid mode) depending on the application requirements, enabling universal memory functionality across different operating conditions.
2Length of moving object
If ReRAM/CBRAM devices are used for non-volatile storage, then scalability to smaller sizes is improved, but resistance switching stability and endurance deteriorate due to fatigue over many cycles
Solution Approach 1:
The patent uses the volatile memory component as an intermediary between the non-volatile memory component and the external interface. The volatile memory buffers and stabilizes the resistance switching operations, reducing the impact of stochastic filament formation and movement on overall system reliability. This intermediary structure allows the system to benefit from the scalability of ReRAM while mitigating its stability issues.
3Ease of operation
If EEPROM devices are used for non-volatile storage, then write/erase capability is achieved, but cell area and voltage requirements increase
Solution Approach 1:
The patent nests the non-volatile memory element within the volatile memory bitcell structure, with the flash memory transistor integrated alongside the DRAM components. This nested arrangement allows the non-volatile storage function to be embedded within the volatile memory footprint, achieving write/erase capability without proportionally increasing the overall cell area.
4Speed
If MRAM devices are used for non-volatile storage, then high write/read speed and endurance are achieved, but power consumption and cost increase
Solution Approach 1:
The patent implements dynamic operation modes where the memory can switch between volatile-only mode (low power), non-volatile-only mode (high speed), and hybrid mode (balanced performance). This dynamic adaptability allows the system to optimize power consumption based on the specific operation requirements, using the high-speed non-volatile path only when necessary rather than continuously.
Data Source
AI summary
Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate transfer of stored values between the volatile and non-volatile memory bitcells.