3D Hybrid Memory Buffer Architecture for Bandwidth and Power

The memory system is segmented into multiple memory tiles stacked vertically, with each tile containing memory arrays and associated logic. This segmentation allows parallel access to multiple tiles simultaneously, thereby increasing overall memory bandwidth while maintaining high capacity through the stacked configuration.

The patent transitions from a planar (2D) memory architecture to a three-dimensional (3D) stacked architecture using through-silicon vias (TSVs). This dimensional change enables vertical stacking of multiple memory tiles, increasing capacity without sacrificing bandwidth, as multiple tiles can be accessed in parallel through the vertical interconnect structure.

Each memory tile is equipped with local refresh logic and power management circuits that operate independently. This local quality approach allows power-efficient refresh operations to be performed at the tile level without requiring system-wide power management, reducing overall power consumption while maintaining high capacity across multiple tiles.

The memory system is divided into independent tiles with separate power domains and refresh logic. This segmentation enables selective powering and refreshing of only the active memory tiles, improving power efficiency by avoiding unnecessary power consumption in inactive regions while maintaining high total capacity.

The patent merges logic process technology benefits (power efficiency and bandwidth) with DRAM process technology benefits (density and capacity) by creating hybrid memory tiles. Each tile combines logic circuits for power management and refresh operations with high-density DRAM arrays, achieving both power efficiency and high memory density simultaneously.

The memory architecture uses a composite structure combining logic circuits and memory arrays in integrated tiles. This composite approach allows the system to leverage the power efficiency and bandwidth advantages of logic technology while maintaining the high density characteristics of DRAM technology, avoiding the trade-off between density and power efficiency.

The through-silicon via structure serves multiple functions: it provides vertical interconnects for data transmission between tiles, carries power and ground signals, and enables thermal management pathways. This multi-functionality reduces the need for separate structures, thereby managing device complexity while achieving high bandwidth through vertical stacking.

The patent resolves the complexity issue by moving interconnects to the vertical dimension through TSVs. Instead of requiring complex lateral routing within a single plane, the 3D architecture uses vertical vias to connect tiles, simplifying the interconnect structure while enabling high bandwidth through parallel access to multiple stacked tiles.

Each memory tile incorporates self-service adaptive refresh logic that automatically monitors and refreshes memory cells based on their actual state and usage patterns. This self-service approach eliminates the need for complex external power management circuits, achieving power efficiency through localized intelligent control without significantly increasing overall device complexity.

The adaptive refresh logic performs preliminary actions by proactively refreshing memory cells before errors occur, based on predicted usage patterns and historical data. This preliminary action approach improves error handling and power efficiency by avoiding reactive corrections, while the localized implementation keeps the added complexity manageable within each tile.