Hybrid Memory Buffer Architecture for DRAM and NAND Flash Integration
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Solution Overview
Problem
Existing computing and data communication systems are inadequate for handling the high demands of modern data transfer, particularly in applications like social networks that process large amounts of multimedia data, due to limitations in traditional memory systems such as high electrical loads on command/address buses and the inability to efficiently support low-latency DRAM and low-cost NAND flash devices within the same memory subsystem.
Innovation Solution
A hybrid memory system architecture that includes a processor coupled to a hybrid memory buffer (HMB) with DRAM and NAND flash modules, utilizing a Memory Storage Controller (MSC) and Near-Memory-Processing (NMP) module via a Serializer/Deserializer (SerDes) interface, which reduces loading through buffering and allows for efficient data movement between DRAM and NAND flash devices without requiring changes to existing CPU memory controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional DIMM architecture with multiple DRAM chips is used, then data bus width and memory capacity are improved, but electrical load on command/address bus increases significantly
Solution Approach 1:
The patent introduces a memory buffer as an intermediary component between the host controller and DRAM chips. This buffer absorbs the electrical load on the command/address bus by providing a localized buffering mechanism that reduces the impact of multiple DRAM chips on the shared CA bus, thereby resolving the contradiction between memory capacity and electrical load.
Solution Approach 2:
The patent segments the memory subsystem into distinct functional components: host controller, memory buffer, and DRAM chips. This segmentation allows the memory buffer to independently manage the electrical loads from multiple DRAM chips, isolating their impact from the shared command/address bus while maintaining high memory capacity.
2Ease of manufacture
If hybrid memory system with both DRAM and NAND flash is used, then cost-effectiveness and storage capacity are improved, but system complexity increases
Solution Approach 1:
The memory buffer is designed with multi-functionality to handle both DRAM and NAND flash memory interfaces. It provides universal support for different memory types through integrated buffering and data movement capabilities, enabling hybrid memory systems without requiring separate dedicated buffers for each memory type, thus reducing overall system complexity.
Solution Approach 2:
The patent merges the buffering functions for DRAM and NAND flash into a single integrated memory buffer unit. This consolidation combines the data movement and load management capabilities for different memory technologies into one component, simplifying the system architecture while maintaining cost-effectiveness through hybrid storage.
3Productivity
If data transfer between DRAM and NAND flash is enabled, then storage bandwidth and productivity are improved, but data movement latency increases
Solution Approach 1:
The memory buffer performs preliminary data buffering and preparation before transferring data between DRAM and NAND flash. By pre-buffering data in the memory buffer's fast memory, the system reduces the latency of data movement by having data ready for immediate transfer, thereby improving productivity while minimizing time loss.
Solution Approach 2:
The memory buffer enables continuous data movement between DRAM and NAND flash by maintaining a persistent buffering mechanism that keeps data flow uninterrupted. This continuous action eliminates idle waiting periods and ensures smooth data transfer, improving bandwidth while minimizing latency through sustained data movement capability.
Data Source
AI summary
A hybrid memory system. This system can include a processor coupled to a hybrid memory buffer (HMB) that is coupled to a plurality of DRAM and a plurality of Flash memory modules. The HMB module can include a Memory Storage Controller (MSC) module and a Near-Memory-Processing (NMP) module coupled by a SerDes (Serializer/Deserializer) interface. This system can utilize a hybrid (mixed-memory type) memory system architecture suitable for supporting low-latency DRAM devices and low-cost NAND flash devices within the same memory sub-system for an industry-standard computer system.