Hybrid Memory Bus Architecture for Bandwidth Without More Pins
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Solution Overview
Problem
Modern computer processors face limitations in memory bus bandwidth due to physical constraints on pins and signal degradation at high speeds, leading to inefficiencies in data transfer rates and increased power consumption.
Innovation Solution
A hybrid memory bus system combining parallel and serial communication channels, where latency-sensitive processors use a parallel bus and latency-insensitive processors utilize a high-speed serial bus, managed by a memory access manager to dynamically route memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory bus width is increased to increase bandwidth, then the data transfer capacity improves, but the number of pins required increases beyond physical limits
Solution Approach 1:
The invention divides the memory bus into multiple separate serial lanes, each transmitting data independently. Instead of using a single wide parallel bus requiring many pins, multiple narrower serial lanes achieve the same total bandwidth with fewer pins per lane, resolving the pin count limitation while maintaining high bandwidth capability
Solution Approach 2:
The invention transitions from a parallel transmission approach (multiple bits simultaneously on multiple conductors) to a serial transmission approach (bits transmitted sequentially on fewer conductors). This dimensional change in data transmission methodology enables high bandwidth without proportionally increasing pin count, as serial lanes can achieve high effective bandwidth through increased transmission speed
2Speed
If the transmission speed of parallel conductors is increased to increase bandwidth, then the data transfer rate improves, but signal degradation from crosstalk and attenuation increases
Solution Approach 1:
By segmenting the data transmission into multiple separate serial lanes rather than using fewer high-speed parallel conductors, each lane operates at lower individual speeds with reduced crosstalk and signal degradation, while the aggregate bandwidth matches that of higher-speed parallel transmission
Solution Approach 2:
The invention replaces the parallel conductor transmission mechanism with serial transmission over separate lanes. This substitution allows for better signal integrity management through reduced electromagnetic interference between adjacent conductors, while achieving equivalent or superior effective bandwidth through optimized serial transmission protocols
3Reliability
If transmission power is increased to reduce signal degradation, then the signal integrity improves, but power consumption increases disproportionately
Solution Approach 1:
By dividing the transmission into multiple lower-speed serial lanes, each lane requires significantly less transmission power to maintain signal integrity compared to a single high-speed parallel conductor. The segmented approach reduces the disproportionate power consumption that would result from increasing power on fewer high-speed lines
4Productivity
If the memory bus width is increased to increase bandwidth, then the data transfer capacity improves, but the skewing and phase shifting of data on separate conductors increases
Solution Approach 1:
By segmenting data transmission into multiple independent serial lanes, each lane maintains its own timing and phase reference without the skewing problems inherent in wide parallel buses. The segmented serial architecture eliminates the data alignment precision issues that arise when increasing parallel bus width, as each serial lane transmits bits sequentially with inherent timing control
Data Source
AI summary
A computer architecture provides both a parallel memory bus and serial memory bus between a processor system and memory. Latency-tolerant memory access requests are steered to the serial memory bus which operates to increase the available memory bus bandwidth on the parallel memory. The invention also provides integrated circuit computer memory suitable for this application.