Hybrid Memory Cache Controller Asynchronous Data Swapping
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Solution Overview
Problem
Current memory systems face inefficiencies in providing high-speed, persistent memory access without requiring hardware modifications, especially in handling data swapping between volatile and non-volatile memory, which can lead to increased processing power consumption and latency.
Innovation Solution
A hybrid memory system incorporating a cache management controller that enables asynchronous communication between volatile and non-volatile memory, allowing data swapping within the memory module without processor intervention, and is compatible with DDR4/DDR5 standards, using a DIMM design that includes flash memory and DRAM, with the volatile memory acting as a cache for non-volatile memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data swapping between volatile and non-volatile memory is performed using traditional memory systems, then persistent memory access is achieved, but processing power consumption and latency increase
Solution Approach 1:
The patent introduces a cache management controller as an intermediary component that autonomously manages data swapping between volatile DRAM and non-volatile flash memory. This controller acts as a mediator that handles memory management tasks without requiring processor intervention, thereby reducing processing power consumption while maintaining persistent memory access capability
Solution Approach 2:
The cache management controller implements self-service by autonomously performing cache line validation, data swapping, and memory management operations without external processor intervention. The controller independently determines which data to swap between memory types and executes these operations autonomously, reducing the energy burden on the processor
2Reliability
If data swapping between volatile and non-volatile memory is performed using traditional memory systems, then persistent memory access is achieved, but latency increases
Solution Approach 1:
The system performs preliminary actions by pre-loading frequently accessed data from non-volatile flash memory into volatile DRAM cache before actual processing occurs. The cache management controller proactively manages data movement based on access patterns, so that when data is needed, it is already in the faster volatile memory, reducing latency
Solution Approach 2:
The cache management controller serves as an intermediary that buffers and manages data transfer between slow non-volatile memory and fast volatile memory. By handling data swapping autonomously and using volatile memory as a buffer, the controller masks the latency of non-volatile memory access from the processor
3Use of energy by moving object
If hybrid memory system with cache management controller is implemented, then processing power consumption is reduced, but device complexity increases
Solution Approach 1:
The cache management controller is designed as a relatively simple intermediary device with dedicated logic for cache line validation and data swapping. Rather than making the processor complex, a separate but simpler control unit is introduced to handle memory management, distributing complexity to where it is most efficient
4Productivity
If asynchronous communication between volatile and non-volatile memory is enabled, then memory access efficiency is enhanced, but device complexity increases
Solution Approach 1:
The system implements dynamic memory management where the cache management controller can independently initiate data swapping operations between volatile and non-volatile memory based on real-time cache validity status. This dynamic, asynchronous operation allows memory efficiency improvements without requiring complex synchronized control from the processor
Data Source
AI summary
In a general aspect, a hybrid memory system with cache management is disclosed. In some aspects, a memory module includes volatile memory, non-volatile memory, and an internal cache. The internal cache is communicably coupled with the volatile memory and the non-volatile memory. Whether to execute a memory access request is determined by operation of the memory module. In response to the inability of the memory access request to be executed, a data transferring process is performed to copy data between the volatile memory and the non-volatile memory via the internal cache.