Hybrid On-Chip Off-Chip Memory Cache Sorting for High-Speed Packet Storage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current packet caching technologies face challenges in achieving high-speed and large-capacity data storage while maintaining low costs, particularly for high-end communication devices that require wire-speed traffic handling, as existing methods such as on-chip caching provide insufficient capacity, off-chip high-speed caching is expensive, and universal DRAM has low read/write efficiency.
Innovation Solution
A system combining on-chip and off-chip memory devices, where the on-chip memory caches and sorts write/read requests, and an off-chip memory device controller writes/reads data according to time sequence restriction information, optimizing data storage and retrieval efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If on-chip memory is used for packet caching, then read/write speed is improved, but cache capacity is limited to below 10 MB
Solution Approach 1:
The patent divides the cache system into two segments: on-chip memory for high-speed access and off-chip memory for large capacity. The on-chip memory handles frequently accessed packets, while the off-chip memory stores less frequently accessed packets, thereby achieving both high speed and large capacity through functional segmentation.
2Speed
If off-chip high-speed memory (SRAM/RLDRAM) is used for packet caching, then cache capacity and read/write speed are improved, but cost increases significantly
Solution Approach 1:
The patent applies local quality by using different memory technologies in different locations within the system. High-speed SRAM or RLDRAM is used only for the on-chip portion that requires fast access, while slower but cheaper universal DRAM is used for the off-chip portion, thereby optimizing the balance between performance and cost.
3Quantity of substance
If off-chip universal DRAM is used for packet caching, then cache capacity and cost are improved, but read/write efficiency decreases
Solution Approach 1:
The patent implements preliminary action by pre-fetching packets from off-chip memory to on-chip memory before they are needed for processing. This proactive data movement ensures that when packets are needed, they are already in the high-speed on-chip memory, thereby maintaining high read/write efficiency despite using slower off-chip universal DRAM for storage.
Data Source
AI summary
A system and a method for writing cache data and a system and a method for reading cache data are disclosed. The system for writing the cache data includes: an on-chip memory device, configured to cache received write requests and write data associated with the write requests and sort the write requests; a request judging device, configured to extract the sorted write requests and the write data associated with the write requests according to write time sequence restriction information of an off-chip memory device; and an off-chip memory device controller, configured to write the write data extracted by the request judging device in the off-chip memory device.