Hybrid Memory System Using CAM for DRAM Refresh Optimization
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Solution Overview
Problem
Conventional DRAMs require frequent refresh cycles to prevent data loss, leading to high system power consumption, and lengthening the refresh cycle can cause data errors.
Innovation Solution
A hybrid memory system combining DRAM and storage-class memory (SCM) with a content addressable memory (CAM) that identifies memory cells with retention times shorter than the DRAM refresh cycle, mapping them to SCM for access to ensure data correctness and reduce power consumption by extending the refresh cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the DRAM refresh cycle is extended to reduce power consumption, then system power consumption is reduced, but data correctness deteriorates due to data errors
Solution Approach 1:
The patent segments the memory system into two parts: DRAM for storing data with retention time longer than the extended refresh cycle, and SCM for storing data with retention time shorter than the extended refresh cycle. This segmentation allows each memory type to handle data appropriate to its characteristics, enabling the DRAM refresh cycle to be extended without compromising data correctness, as data that would otherwise fail within the extended cycle is stored in SCM instead.
Solution Approach 2:
The patent introduces a CAM (Content Addressable Memory) as an intermediary component that stores mapping relationships between DRAM addresses and SCM addresses. When the memory controller needs to access data, the CAM quickly determines whether the data should be accessed from DRAM or SCM based on retention time characteristics. This intermediary enables intelligent data placement and access routing, ensuring data correctness while allowing extended DRAM refresh cycles.
2Use of energy by stationary object
If the DRAM refresh frequency is lowered to reduce power consumption, then system power consumption is reduced, but data loss increases
Solution Approach 1:
The patent divides the memory storage function between DRAM and SCM based on data retention characteristics. Data that would be lost during the extended refresh cycle in conventional DRAM is instead stored in SCM, which maintains data integrity without requiring frequent refreshes. This segmentation prevents data loss while enabling lower refresh frequency in DRAM, thereby reducing refresh power consumption.
Solution Approach 2:
The patent changes the refresh cycle parameter of DRAM from the conventional 64ms to an extended period (such as 128ms or longer). By combining this parameter change with the introduction of SCM to handle data with short retention times, the system achieves lower refresh power consumption without incurring data loss, as the extended refresh cycle only applies to data that can maintain retention for that duration.
3Use of energy by stationary object
If a hybrid memory system with SCM is introduced to reduce refresh power consumption, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent introduces CAM as an intermediary component that manages the complexity of the hybrid memory system. The CAM stores compact mapping relationships between DRAM and SCM addresses, enabling the memory controller to quickly determine whether to access data from DRAM or SCM. This intermediary simplifies the control logic compared to more complex management schemes, as it provides a direct address-mapping mechanism that integrates seamlessly with existing memory controllers while enabling intelligent data placement.
Solution Approach 2:
The patent designs the hybrid memory system to maintain compatibility with existing memory interfaces and protocols. The memory controller continues to operate using standard DRAM access commands, while the CAM and SCM work together in the background to handle data with short retention times. This multi-functionality approach allows the system to reduce refresh power consumption without requiring complete redesign of the memory subsystem, thereby limiting the increase in device complexity.
Data Source
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AI summary
Embodiments of the present invention provide a memory access method, a storage-class memory, and a computer system. The computer system includes a memory controller and a hybrid memory, and the hybrid memory includes a dynamic random access memory DRAM and a storage-class memory SCM. The memory controller is configured to send a first access instruction to the DRAM and the SCM. When determining that a first memory cell set that is of the DRAM and to which a first address in the received first access instruction points includes a memory cell whose retention time is shorter than a refresh cycle of the DRAM, the SCM may obtain a second address having a mapping relationship with the first address. Further, the SCM converts, according to the second address, the first access instruction into a second access instruction for accessing the SCM, to implement access to the SCM. The computer system provided in the embodiments of the present invention can ensure correctness of data while reducing power consumption for DRAM refresh.