Hybrid Memory Capacitor Layout for Speed and Data Retention
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Solution Overview
Problem
Current memory devices face limitations due to the trade-offs between volatile and non-volatile memory types, where choosing one over the other can result in reduced performance in certain metrics, such as latency, power consumption, and storage duration, especially in power- and space-sensitive devices like mobile devices.
Innovation Solution
A hybrid memory device is developed that combines volatile and non-volatile memory cells, such as DRAM and FeRAM, on a single substrate, allowing for fast read/write operations and long-term storage, reducing latency and power requirements, and optimizing area usage by integrating both types within a single memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If volatile memory (DRAM) is used, then read/write speed is improved, but data retention duration deteriorates
Solution Approach 1:
The memory device is divided into two separate memory arrays: a first memory array using volatile memory (DRAM) for fast read/write operations, and a second memory array using non-volatile memory (FeRAM) for long-term data retention. This segmentation allows each memory type to operate in its optimal performance regime without compromising the other.
2Duration of action of stationary object
If non-volatile memory (FeRAM) is used, then data retention duration is improved, but read/write speed deteriorates
Solution Approach 1:
The memory device is divided into two separate memory arrays: a first memory array using volatile memory (DRAM) for fast read/write operations, and a second memory array using non-volatile memory (FeRAM) for long-term data retention. This segmentation allows each memory type to operate in its optimal performance regime without compromising the other.
3Duration of action of stationary object
If separate memory arrays for volatile and non-volatile memory are used, then data retention is improved, but device complexity increases
Solution Approach 1:
The patent combines both volatile (DRAM) and non-volatile (FeRAM) memory arrays into a single hybrid memory device with unified control circuitry. This merging approach integrates the benefits of both memory types while reducing the overall system complexity compared to using separate discrete memory devices.
Solution Approach 2:
The hybrid memory device provides multi-functional capabilities by supporting both volatile and non-volatile memory operations within a single device architecture. The control circuitry is designed to manage both memory types universally, allowing the device to adapt to different application requirements without needing separate specialized memory devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hybrid memory device enhances performance by reducing latency and power consumption, improving endurance, and eliminating the need for separate memory arrays, thus offering improved data transfer speeds and extended storage capabilities while minimizing the need for additional power components.
Implementation Method 1
A first memory cell may include a first capacitor and a first transistor. The first capacitor may be configured to store a logic value
Implementation Method 2
A second memory cell may include a second capacitor and a second transistor. The second capacitor may be configured to store a logic value
Data Source
AI summary
The hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.